Zilog Z80180 Manual de usuario Pagina 1

ZiLOG WORLDWIDE HEADQUARTERS • 532 Race Street • SAN JOSE, CA 95126-3432TELEPHONE: 408.558.8500 • FAX: 408.558.8300 • WWW.ZILOG.COMZ8018xFamily MPUUse

Z8018xFamily MPU User ManualUM005003-0703xiFigure 49. TEND0 Output Timing Diagram . . . . . . . . . . . . . . . . . . .108Figure 50. DMA Interrupt R

Z8018xFamily MPU User Manual UM005003-070385Z8X180. Figure 43 illustrates the INT1, INT2 and internal interrupts timi

Z8018xFamily MPU User Manual86UM005003-0703 Figure 43. INT1, INT2 and Internal Interrupts Timing DiagramDynamic RAM Refresh

Z8018xFamily MPU User Manual UM005003-070387Refresh cycles may be programmed to be either two or three clock cycles i

Z8018xFamily MPU User Manual88UM005003-0703 Refresh Control Register (RCR)The RCR specifies the interval and length of refre

Z8018xFamily MPU User Manual UM005003-070389Refresh Control And RESETAfter RESET, based on the initialized value of R

Z8018xFamily MPU User Manual90UM005003-0703 3. Refresh cycles are suppressed during SLEEP mode. If a refresh cycle is reques

Z8018xFamily MPU User Manual UM005003-070391•DREQ InputLevel- and edge-sense DREQ input detection are selectable.TEND

Z8018xFamily MPU User Manual92UM005003-0703 Channel 0 •SAR0–Source Address Register•DAR0–Destination Address Register •BCR0–

Z8018xFamily MPU User Manual UM005003-070393Figure 45. DMAC Block DiagramDMAC Register DescriptionDMA Source Address

Z8018xFamily MPU User Manual94UM005003-0703 DMA Destination Address Register Channel 0 (DAR0 I/O Address = 23H to 25H)Specif

Z8018xFamily MPU User ManualUM005003-0703xiiSoftware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173Figure 74.

Z8018xFamily MPU User Manual UM005003-070395DMA Status Register (DSTAT)DSTAT is used to enable and disable DMA transf

Z8018xFamily MPU User Manual96UM005003-0703 6DE0R/W Enable Channel 0 — When DE0 = 1 and DME = 1, channel 0 DMA is enabled. W

Z8018xFamily MPU User Manual UM005003-070397DMA Mode Register (DMODE) DMODE is used to set the addressing and transfe

Z8018xFamily MPU User Manual98UM005003-0703 3–2SM1:0W Source Mode Channel — Specifies whether the source for channel 0 trans

Z8018xFamily MPU User Manual UM005003-070399Table 14 describes all DMA TRANSFER mode combinations of DM0 DM1, SM0 SM1

Z8018xFamily MPU User Manual100UM005003-0703 DMA/WAIT Control Register (DCNTL)DCNTL controls the insertion of Wait States in

Z8018xFamily MPU User Manual UM005003-0703101DMA/WAIT Control Register (DCNTL: 32H)Bit 76543210Bit/Field MWI1 MWI0 IW

Z8018xFamily MPU User Manual102UM005003-0703 Table 15. Channel 1 Transfer ModeDIM1 DIM0 Transfer Mode Address Increment/Dec

Z8018xFamily MPU User Manual UM005003-0703103DMA Register DescriptionBit 7This bit must be set to 1 only when both DM

Z8018xFamily MPU User Manual104UM005003-0703 Bits 5–3Reserved. Must be 0.Bits 2–0With DIM1, bit 1 of DCNTL, these bits contr

Z8018xFamily MPU User ManualUM005003-0703xivList of TablesZ80180, Z8S180, Z8L180 MPU Operation . . . . . . . . . . . . . . . . . . . .1Table 1. Stat

Z8018xFamily MPU User Manual UM005003-0703105In addition, the operation of channel 0 DMA with the on-chip ASCI (Async

Z8018xFamily MPU User Manual106UM005003-0703 Figure 46. DMA Timing Diagram-CYCLE STEAL ModeTo initiate memory to/from memory

Z8018xFamily MPU User Manual UM005003-0703107Memory to I/O (Memory Mapped I/O) — Channel 0 For memory to/from I/O (an

Z8018xFamily MPU User Manual108UM005003-0703 rising edge of the clock prior to T3 at which time the DMA operation (re)starts

Z8018xFamily MPU User Manual UM005003-0703109memory mapped I/O. transfers, the CKA0/DREQ0 pin automatically functions

Z8018xFamily MPU User Manual110UM005003-0703 DREQ0 for ASCI transmission and reception respectively. To initiate memory to/f

Z8018xFamily MPU User Manual UM005003-07031112. Specify memory « I/O transfer mode and address increment/decrement in

Z8018xFamily MPU User Manual112UM005003-0703 4. Specify whether DREQ1 is level- or edge- sense in the DMS1 bit in DCNTL.5. E

Z8018xFamily MPU User Manual UM005003-0703113cycle is extended to 4 clocks by automatic insertion of one internal Ti

Z8018xFamily MPU User Manual114UM005003-0703 DMAC Internal InterruptsFigure 50 illustrates the internal DMA interrupt reques

Z8018xFamily MPU User ManualUM005003-0703xvTable 23. Timer Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .163Table 24. E Clock

Z8018xFamily MPU User Manual UM005003-0703115If the falling edge of NMI occurs before the falling clock of the state

Z8018xFamily MPU User Manual116UM005003-0703 The key functions for ASCI on Z80180, Z8S180 and Z8L180 class processors are li

Z8018xFamily MPU User Manual UM005003-0703117Figure 52. ASCI Block DiagramASCI Register DescriptionThe following subp

Z8018xFamily MPU User Manual118UM005003-0703 When transmission is completed, the next byte (if available) is automatically l

Z8018xFamily MPU User Manual UM005003-0703119ASCI Receive Shift Register 0,1(RSR0, 1)This register receives data shif

Z8018xFamily MPU User Manual120UM005003-0703 0, data can be written into the ASCII Receive Data Register, and the data can b

Z8018xFamily MPU User Manual UM005003-07031215PER Parity Error — PE is set to 1 when a parity error is detected on an

Z8018xFamily MPU User Manual122UM005003-0703 0TIER/W Transmit Interrupt Enable — TIE must be set to 1 to enable ASCI transmi

Z8018xFamily MPU User Manual UM005003-0703123ASCI Control Register A0, 1 (CNTLA0, 1)Each ASCI channel Control Registe

Z8018xFamily MPU User Manual124UM005003-0703 4FER Framing Error — If a receive data byte frame is delimited by an invalid st

Z8018xFamily MPU User ManualUM005003-0703xviTable 43. Block Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225Table 44.

Z8018xFamily MPU User Manual UM005003-0703125ASCI Control Register A0, 1 (CNTLA0, 1)Each ASCI channel Control Registe

Z8018xFamily MPU User Manual126UM005003-0703 6RER/W Receiver Enable — When RE is set to 1, the ASCI receiver is enabled. Whe

Z8018xFamily MPU User Manual UM005003-07031272–0 MOD2–0R/W ASCI Data Format Mode 2, 1, 0 — These bits program the ASC

Z8018xFamily MPU User Manual128UM005003-0703 ASCI Control Register A 1 (CNTLA1: 01H)Bit 76543210Bit/Field MPE RE TE CKA1D MP

Z8018xFamily MPU User Manual UM005003-07031295TER/W Transmitter Enable — When TE is set to 1, the ASCI transmitter is

Z8018xFamily MPU User Manual130UM005003-0703 2–0 MOD2–0R/W ASCI Data Format Mode 2, 1, 0 — These bits program the ASCI data

Z8018xFamily MPU User Manual UM005003-0703131ASCI Control Register B0, 1 (CNTLB0, 1)Each ASCI channel control registe

Z8018xFamily MPU User Manual132UM005003-0703 ASCI Control Register B 0 (CNTLB0: 02H)ASCI Control Register B 1 (CNTLB1: 03H)B

Z8018xFamily MPU User Manual UM005003-0703133The external ASCI channel 0 data clock pins are multiplexed with DMA con

Z8018xFamily MPU User Manual134UM005003-0703 pins are initialized as ASCI data clock inputs. If SS2, SS1 and SS0 are reprogr

Z8018xFamily MPU User ManualUM005003-0703xv

Z8018xFamily MPU User Manual UM005003-0703135ASCI0 Extension Control Register (I/O Address: 12H) (Z8S180/L180-Class P

Z8018xFamily MPU User Manual136UM005003-0703 Each ASCI channel control register B configures multiprocessor mode, parity and

Z8018xFamily MPU User Manual UM005003-0703137Each ASCI channel control register B configures multiprocessor mode, par

Z8018xFamily MPU User Manual138UM005003-0703 Modem Control SignalsASCI channel 0 has CTS0, DCD0 and RTS0 external modem cont

Z8018xFamily MPU User Manual UM005003-0703139The error flags (PE, FE, and OVRN bits) are also held at 0. Even after t

Z8018xFamily MPU User Manual140UM005003-0703 Figure 54. RTS0 Timing DiagramFigure 55 illustrates the ASCI interrupt request

Z8018xFamily MPU User Manual UM005003-0703141ASCI to/from DMAC OperationOperation of the ASCI with the on-chip DMAC c

Z8018xFamily MPU User Manual142UM005003-0703 Table 19. ASCI Baud Rate SelectionPrescalerSamplingRate Baud RateGeneralDivide

Z8018xFamily MPU User Manual UM005003-0703143Baud Rate Generator(Z8S180/Z8L180-Class Processors Only)The Z8S180/Z8L18

Z8018xFamily MPU User Manual144UM005003-0703 a common baud rate of up to 512 Kbps to be selected. The BRG can also be disabl

Z8018xFamily MPU User Manual1 UM005003-0703Z80180, Z8S180, Z8L180 MPU OperationFEATURES•Operating Frequency to 33

Z8018xFamily MPU User Manual UM005003-07031452^ss depends on the three least significant bits of the CNTLB register,

Z8018xFamily MPU User Manual146UM005003-0703 causes for an ASCI Receive interrupt (PE, FE, OVRN, and for ASCI0, DCD) continu

Z8018xFamily MPU User Manual UM005003-0703147Figure 57. CSI/O Block DiagramCSI/O Registers DescriptionCSI/O Control/S

Z8018xFamily MPU User Manual148UM005003-0703 BitPosition Bit/Field R/W Value Description7EFR End Flag — EF is set to 1 by th

Z8018xFamily MPU User Manual UM005003-0703149CSI/O Transmit/Receive Data Register (TRDR: I/O Address = 0BH).TRDR is u

Z8018xFamily MPU User Manual150UM005003-0703 After RESET, the CKS pin is configured as an external clock input (SS2, SS1, SS

Z8018xFamily MPU User Manual UM005003-0703151Figure 58. CSI/O Interrupt Request GenerationCSI/O OperationThe CSI/O is

Z8018xFamily MPU User Manual152UM005003-0703 c. Poll the RE bit in CNTR until RE = 0.d. Read the receive data from TRDR.e. R

Z8018xFamily MPU User Manual UM005003-0703153CSI/O and RESETDuring RESET each bit in the CNTR is initialized as defin

Z8018xFamily MPU User Manual154UM005003-0703 Figure 60. Transmit Timing–External ClockCKSTXSTEEFRead or write of CSI/OTransm

Z8018xFamily MPU User Manual2UM005003-0703 on-chip memory management unit (MMU) with the capability of addressing up to 1 MB

Z8018xFamily MPU User Manual UM005003-0703155Figure 61. CSI/O Receive Timing–Internal ClockCKSRXSREEFRead or write of

Z8018xFamily MPU User Manual156UM005003-0703 Figure 62. CSI/O Receive Timing–External ClockProgrammable Reload Timer (PRT)Th

Z8018xFamily MPU User Manual UM005003-0703157control register. The PRT input clock for both channels is equal to the

Z8018xFamily MPU User Manual158UM005003-0703 return accurate data without requiring the timer to be stopped. The write proce

Z8018xFamily MPU User Manual UM005003-0703159Timer Reload Register (RLDR: I/O Address = CH0: 0EH, 0FH, CHI, 16H, 17H)

Z8018xFamily MPU User Manual160UM005003-0703 Timer Reload Register Channel 0L (RLDR0L: 0EH)Bit 76543210Bit/Field Timer Reloa

Z8018xFamily MPU User Manual UM005003-0703161Timer Control Register (TCR)TCR monitors both channels (PRT0, PRT1) TMDR

Z8018xFamily MPU User Manual162UM005003-0703 BitPosition Bit/Field R/W Value Description7–6TIF1–0R TIF1: Timer Interrupt Fla

Z8018xFamily MPU User Manual UM005003-0703163Figure 64 illustrates timer initialization, count down, and reload timin

Z8018xFamily MPU User Manual164UM005003-0703 Figure 65. Timer Output Timing DiagramPRT InterruptsThe PRT interrupt request c

Z8018xFamily MPU User Manual UM005003-07033Figure 1. 64-Pin DIPVSSXTALEXTALWAITBUSACKBUSREQRESETNMIINT0INT1INT2STA0A1

Z8018xFamily MPU User Manual UM005003-0703165PRT Operation Notes•TMDR data is accurately read without stopping down c

Z8018xFamily MPU User Manual166UM005003-0703 These devices require connection with the Z8X180 synchronous E clock output. Th

Z8018xFamily MPU User Manual UM005003-0703167Figure 67. E Clock Timing Diagram (During Read/Write Cycle and Interrupt

Z8018xFamily MPU User Manual168UM005003-0703 Figure 69. E Clock Timing in SLEEP Mode and SYSTEM STOP ModeOn-Chip Clock Gener

Z8018xFamily MPU User Manual UM005003-0703169If an external clock input is used instead of a crystal, the waveform (t

Z8018xFamily MPU User Manual170UM005003-0703 Figure 71. Clock Generator CircuitFigure 72. Circuit Board Design RulesZ8X180XT

Z8018xFamily MPU User Manual UM005003-0703171Figure 73. Example of Board DesignCircuit Board design should observe th

Z8018xFamily MPU User Manual172UM005003-0703 MiscellaneousFree Running Counter (I/O Address = 18H)If data is written into th

Z8018xFamily MPU User Manual173 UM005003-0703Software ArchitectureINSTRUCTION SETThe Z80180 is object code-compati

Z8018xFamily MPU User Manual174UM005003-0703 MLT- MultiplyThe MLT performs unsigned multiplication on two 8-bit numbers yiel

Z8018xFamily MPU User Manual4UM005003-0703 Figure 2. 68-Pin PLCCA15A16A17A18/TOUTVCCA19VSSD0D1D2D3D4D5D627282930323334353631

Z8018xFamily MPU User Manual UM005003-0703175TST (HL) - Test MemoryThe contents of memory pointed to by HL are ANDed

Z8018xFamily MPU User Manual176UM005003-0703 Figure 74 depicts CPU register configurations.Figure 74. CPU Register Configura

Z8018xFamily MPU User Manual UM005003-0703177Flag Registers (F, F')The flag registers store status bits (describ

Z8018xFamily MPU User Manual178UM005003-0703 Stack Pointer (SP)The Stack Pointer (SP) contains the memory address based LIFO

Z8018xFamily MPU User Manual UM005003-07031796Z R/W0Zero.Z is set to 1 when instruction execution produces 0 result.

Z8018xFamily MPU User Manual180UM005003-0703 Addressing ModesThe Z80180 instruction set includes eight addressing modes.•Imp

Z8018xFamily MPU User Manual UM005003-0703181Figure 75. Register Direct — Bit Field DefinitionsRegister Indirect (REG

Z8018xFamily MPU User Manual182UM005003-0703 Indexed (INDX)The memory operand address is calculated using the contents of an

Z8018xFamily MPU User Manual UM005003-0703183Immediate (IMMED)The memory operands are contained within one or two byt

Z8018xFamily MPU User Manual184UM005003-0703 IO (I/O)IO addressing mode is used only by I/O instructions. This mode specifie

Z8018xFamily MPU User ManualUM005003-0703This publication is subject to replacement by a later edition. To determine whether a later edition exists, o

Z8018xFamily MPU User Manual UM005003-07035Figure 3. 80-Pin QFPZ8X180STA0A1A2A3VSSA4NCA5A6A71234678910511121314151617

Z8018xFamily MPU User Manual185 UM005003-0703DC CharacteristicsThis section describes the DC characteristics of th

Z8018xFamily MPU User Manual186UM005003-0703 Z80180 DC CHARACTERISTICSVCC = 5V ± 10%, VSS = OV, Ta = 0° to +70°C, unless otherwis

Z8018xFamily MPU User Manual UM005003-0703187Z8S180 DC CHARACTERISTICSVCC = 5V ± 10%, VSS = OV, Ta = 0° to +70°C, unl

Z8018xFamily MPU User Manual188UM005003-0703 VOH1 Output High VoltageAll outputsIOH = –200 mAIOH = –20 mA2.4VCC –1.2––––VVVOH2 Ou

Z8018xFamily MPU User Manual UM005003-0703189Z8L180 DC CHARACTERISTICSVCC = 3.3V ± 10%, VSS = OV, Ta = 0° to +70°C, u

Z8018xFamily MPU User Manual190UM005003-0703 ICC Power Dissipation*(Normal Operation)f = 20 MHz 20 100 mAPower Dissipation*(SYSTE

Z8018xFamily MPU User Manual UM005003-0703191543212.73.03.3VDD (Volts)ICC Active (mA.)Typical ICCA at 4 MHzZ8L1805040

Z8018xFamily MPU User Manual192UM005003-0703

Z8018xFamily MPU User Manual193 UM005003-0703AC CharacteristicsThis section describes the AC characteristics of th

Z8018xFamily MPU User Manual194UM005003-0703 12 tMED2PHI Fall to MREQ Rise Delay — 25 — 15 ns13 tRDD2PHI Fall to RD Rise Del

Z8018xFamily MPU User Manual6UM005003-0703 Figure 4. Z80180/Z8S180/Z8L180 Block DiagramMMUAddress BufferData BufferA0–A19D0–

Z8018xFamily MPU User Manual UM005003-070319531 tINTSINT Set-up Time to PHI Fall 20 — 15 — ns32 tINTHINT Hold Time fr

Z8018xFamily MPU User Manual196UM005003-0703 54 tEfEnable Fall Time — 10 — 10 ns55 tTODPHI Fall to Timer Output Delay — 75 —

Z8018xFamily MPU User Manual UM005003-070319769 tIRInput Rise Time (except EXTAL, RESET)—50—50 ns70 tIFInput Fall Tim

Z8018xFamily MPU User Manual197 UM005003-0703Timing DiagramsFigure 81. AC Timing Diagram 1PHIADDRESSWAITMREQIORQRD

Z8018xFamily MPU User Manual198UM005003-0703 Memory Read/Write Cycle timing is the sam as I/O Read/Write Cycle except there

Z8018xFamily MPU User Manual UM005003-0703199Figure 83. CPU Timing (IOC = 0) (I/O Read Cycle, I/O Write Cycle)T1T2TwT

Z8018xFamily MPU User Manual200UM005003-0703 Figure 84. DMA Control Signals4745 464818(level sense)DREQ1(edge sense)TENDiSTP

Z8018xFamily MPU User Manual UM005003-0703201Figure 85. E Clock Timing (Memory R/W Cycle) (I/O R/W Cycle)Figure 86. E

Z8018xFamily MPU User Manual202UM005003-0703 Figure 87. E Clock Timing (Minimum Timing Example of PWEL and PWEH)Figure 88. T

Z8018xFamily MPU User Manual UM005003-0703203Figure 89. SLP Execution Cycle Timing Diagram32444333A19–A0SLP Instructi

Z8018xFamily MPU User Manual UM005003-07037PIN DESCRIPTIONA0–A19. Address Bus (Output, Active High, 3-state). A0–A19

Z8018xFamily MPU User Manual204UM005003-0703 Figure 90. CSI/O Receive/Transmit Timing DiagramFigure 91. External Clock Rise

Z8018xFamily MPU User Manual UM005003-0703205STANDARD TEST CONDITIONSThe previous DC Characteristics and Capacitance

Z8018xFamily MPU User Manual206UM005003-0703

Z8018xFamily MPU User Manual207 UM005003-0703Instruction SetThis section explains the symbols in the instruction s

Z8018xFamily MPU User Manual208UM005003-0703 CONDITIONf specifies the condition in program control instructions. Table 34 de

Z8018xFamily MPU User Manual UM005003-0703209RESTART ADDRESSv specifies a restart address. Table 35 describes the

Z8018xFamily MPU User Manual210UM005003-0703 MISCELLANEOUSTable 37 lists the operations mnemonics.Table 37. Operations Mnem

Z8018xFamily MPU User Manual UM005003-0703211DATA MANIPULATION INSTRUCTIONSTable 38. Arithmetic and Logical Instr

Z8018xFamily MPU User Manual212UM005003-0703 AND AND g 10 100 g S D 1 4 Ar*gr®Ar SP RRAND (HL) 10 100 110 S D 1 6 Ar*(HL)M

Z8018xFamily MPU User Manual UM005003-0703213DEC DEC g 00 g 101 S/D 1 4 gr-1®gr VS·DEC (HL) 00 110 101 S/D 1 10

Z8018xFamily MPU User Manual8UM005003-0703 D0–D7. Data Bus (Bidirectional, Active High, 3-state). D0-D7 constitute an 8-bit

Z8018xFamily MPU User Manual214UM005003-0703 OR OR g 10 110 g S D 1 4 Ar + gr®Ar RP RROR (HL) 10 110 110 S D 1 6 Ar + (HL)

Z8018xFamily MPU User Manual UM005003-0703215SUBC SBC A,g 10 011 g S D 1 4 Ar-gr-c®Ar VSSBC A,(HL) 10 011 110

Z8018xFamily MPU User Manual216UM005003-0703 XOR (IY + d) 11 111 101 S D 3 14ArÅ + (IY + d))M®ArRP RR10 101 110<d>Ta

Z8018xFamily MPU User Manual UM005003-0703217RLC (IX + d) 11 011 101 S/D 4 19 RP R11 001 011<d>00 000 110

Z8018xFamily MPU User Manual218UM005003-0703 11 001 011<d>00 001 110RRD 11 101 101 S/D 2 16 RP R·01 100 111SLA g 11

Z8018xFamily MPU User Manual UM005003-0703219SRL (HL) 11 001 011 S/D 2 3 RP R00 111 110SRL (IX + d) 11 011 101

Z8018xFamily MPU User Manual220UM005003-0703 Bit Reset RES b,(IY + d) 11 011 101 S/D 4 19 0®b·(IY + d)M···· ··11 001 01l<

Z8018xFamily MPU User Manual UM005003-0703221Table 40. Arithmetic Instructions (16-bit)OperationName Mnemonics Op

Z8018xFamily MPU User Manual222UM005003-0703 DATA TRANSFER INSTRUCTIONSTable 41. 8-Bit LoadOperationName Mnemonics Op CodeA

Z8018xFamily MPU User Manual UM005003-0703223Load8-BitDataLD (IX + d),m 11 011 101 S D 4 15 m®(IX + d)M···· ··00 1

Z8018xFamily MPU User Manual UM005003-07039BUSREQ, and INT0 signals are inactive. The CPU acknowledges these interrup

Z8018xFamily MPU User Manual224UM005003-0703 Load16-Bit DataLD IY,mn 11 111 101 S D 4 12 mn®IYR···· ··00 100 001<n><

Z8018xFamily MPU User Manual UM005003-0703225Load16-bitDataLD (mn),HL 00 100 010 D S 3 16 Hr®(mn + 1)M···· ··<n

Z8018xFamily MPU User Manual226UM005003-0703 CPI 11101101 S S 2 12 Ar-(HL)M  S ·10100001 BCR-1®BCRHLR + 1®HLR(3) (2)CPIR

Z8018xFamily MPU User Manual UM005003-0703227Table 44. Stock and ExchangeOperationName Mnemonics Op CodeAddressin

Z8018xFamily MPU User Manual228UM005003-0703 .Exchange EX AFAF’ 00 001 000 S/D 1 4 AFR-AFR' ···· ··EX DE, HL 11 101 011

Z8018xFamily MPU User Manual UM005003-0703229PROGRAM AND CONTROL INSTRUCTIONSTable 45. Program Control Instructio

Z8018xFamily MPU User Manual230UM005003-0703 Jump JR Zj 00 101 000 D 2 6 continue : Z = 0 ···· ··<j-2> 28 PCR, + j®PCR

Z8018xFamily MPU User Manual UM005003-0703231Table 46. I/O InstructionsOperationName Mnemonics Op CodeAddressingB

Z8018xFamily MPU User Manual232UM005003-0703 INPUT INIR 11 101 101 D S 2 14 (Br ¹ 0) (BC)I®(HL)MQ HLR + 1®HLRBr-f®BrXS XX 

Z8018xFamily MPU User Manual UM005003-0703233OUTPUT OTDR 11 101 101 S D 2 14 (Br ¹ 0) (HL)M®(BC)M1QHLR-1®HLRBr-1Br

Z8018xFamily MPU User Manual10UM005003-0703 RTS0. Request to Send 0 (Output, Active Low). This output is a programmable mode

Z8018xFamily MPU User Manual234UM005003-0703 OTIMR** 11 101 101 S D 2 16 (Br ¹ 0) (HL)M®(00C)IHLR + 1®HLRQCr + 1®CrBr-1®BrRS

Z8018xFamily MPU User Manual UM005003-0703235Special Control InstructionsTable 47. Special Control InstructionsOp

Z8018xFamily MPU User Manual236UM005003-0703

Z8018xFamily MPU User Manual237 UM005003-0703Instruction Summary** : Added new instructions to Z80MNEMONICS BytesM

Z8018xFamily MPU User Manual238UM005003-0703 3616(If condition is true)CALL mn 3 6 16CCF 1 1 3CPD 2 6 12CPDR 2 8 14(If BCR ¹

Z8018xFamily MPU User Manual UM005003-07032392 3 7 (if Br = 0)EI 1 1 3EX AF,AF' 1 2 4EX DE,HL 1 1 3EX (SP),HL

Z8018xFamily MPU User Manual240UM005003-0703 339(If f is true)JP (HL) 1 1 3JP (IX) 2 2 6JP (IY) 2 2 6JP mn 3 3 9JR j 2 4 8JR

Z8018xFamily MPU User Manual UM005003-0703241LD (DE),A 1 3 7LD ww,mn 3 3 9LD ww,(mn) 4 6 18LDDR 2 6 14 (If BCR ¹ 0

Z8018xFamily MPU User Manual242UM005003-0703 LD g,g' 1 2 4LD SP,HL 1 2 4LD SP,IX 2 3 7LD SP,IY 2 3 7MLT ww" 2 13 1

Z8018xFamily MPU User Manual UM005003-0703243PUSH IX 2 6 14PUSH IY 2 6 14PUSH zz 1 5 11RES b,(HL) 2 5 13RES b,(IX+

Z8018xFamily MPU User Manual UM005003-070311TOUT. Timer Out (Output, Active High). TOUT is the pulse output from PRT

Z8018xFamily MPU User Manual244UM005003-0703 RRC (IY+d) 4 7 19RRC g 2 3 7RRD 2 8 16RR (HL) 2 5 13RR (IX+d) 4 7 19RR (IY+d) 4

Z8018xFamily MPU User Manual UM005003-0703245SRL (IY+d) 4 7 19SRL g 2 3 7SUB (HL) 1 2 6SUB (IX+d) 3 6 14SUB (IY+d)

Z8018xFamily MPU User Manual246UM005003-0703

Z8018xFamily MPU User Manual247 UM005003-0703Op Code MapTable 48. 1st Op Code Map Instruction Format: XXww (L0 =

Z8018xFamily MPU User Manual248UM005003-0703Note 1: (HL) replaces g.Note 2: (HL) replaces s.Note 3: If DDH is supplemented as first Op Code for the in

Z8018xFamily MPU User Manual UM005003-0703249Table 49. 2nd Op Code Map Instruction Format: CB XXb (L0 = 0~7)02460246

Z8018xFamily MPU User Manual250UM005003-0703Table 50. 2nd Op Code Map Instruction Format: ED XXww (L0 = ALL)BC DE HL SPG (L0 = 0~7)BDH BD H0000 0001

Z8018xFamily MPU User Manual251 UM005003-0703Bus Control Signal ConditionsBUS AND CONTROL SIGNAL CONDITION IN EACH

Z8018xFamily MPU User Manual252UM005003-0703 ADD A,g ADC A,gSUB g SBC A,gAND gOR gXOR gCP gMC1 T1T2T3 1st Op Code Address1st

Z8018xFamily MPU User Manual UM005003-0703253AND (IY+ d)OR (IX + d)OR (IY+d)XOR (IX + d)XOR (IY+d)MC4~MC6TiTiTi * Z 1

Z8018xFamily MPU User Manual12UM005003-0703 ARCHITECTUREThe Z8X180 combines a high performance CPU core with a variety of sy

Z8018xFamily MPU User Manual254UM005003-0703 CALL mnMC1 T1T2T3 1st Op Code Address1st Op Code010 1 01 0MC2 T1T2T3 1st operan

Z8018xFamily MPU User Manual UM005003-0703255CPICPDMC1 T1T2T3 1st Op Code Address1st Op Code010 1 01 0MC2 T1T2T3 2nd

Z8018xFamily MPU User Manual256UM005003-0703 DJNZ j(If Br ¹ 0)MC1 T1T2T3 1st Op Code Address1st Op Code010 1 01 0MC2 Ti*2 *

Z8018xFamily MPU User Manual UM005003-0703257EX (SP),IXEX (SP),IYMC1 T1T2T3 1st Op Code Address1st Op Code010 1 01 0M

Z8018xFamily MPU User Manual258UM005003-0703 INC (IX+ d)INC (IY+d)DEC (IX+d)DEC (IY+d)MC1 T1T2T3 1st Op Code Address1st Op C

Z8018xFamily MPU User Manual UM005003-0703259IN g,(C)MC1 T1T2T3 1st Op Code Address1st Op Code010 1 01 0MC2 T1T2T3 2n

Z8018xFamily MPU User Manual260UM005003-0703 INIRINDR(If Br=0)MC1 T1T2T3 1st Op Code Address1st Op Code010 1 01 0MC2 T1T2T3

Z8018xFamily MPU User Manual UM005003-0703261JR jMC1 T1T2T3 1st Op Code Address1st Op Code010 1 01 0MC2 T1T2T3 1st op

Z8018xFamily MPU User Manual262UM005003-0703 LD g, (IX+d)LD g, (IY+d)MC1 T1T2T3 1st Op Code Address1st Op Code010 1 01 0MC2

Z8018xFamily MPU User Manual UM005003-0703263LD (IX+d),mLD (IY+d),mMC1 T1T2T3 1st Op Code Address1st Op Code010 1 01

Z8018xFamily MPU User Manual UM005003-070313•Programmable Reload Timers (PRT, 2 channels)•Clock Serial I/O (CSIO) cha

Z8018xFamily MPU User Manual264UM005003-0703 LD (mn),AMC1 T1T2T3 1st Op Code Address1st Op Code010 1 01 0MC2 T1T2T3 1st oper

Z8018xFamily MPU User Manual UM005003-0703265LD HL, (mn)MC1 T1T2T3 1st Op Code Address1st Op Code010 1 01 0MC2 T1T2T3

Z8018xFamily MPU User Manual266UM005003-0703 LD (mn),HLMC1 T1T2T3 1st Op Code Address1st Op Code010 1 01 0MC2 T1T2T3 1st ope

Z8018xFamily MPU User Manual UM005003-0703267LD (mn),IXLD (mn),IYMC1 T1T2T3 1st Op Code Address1st Op Code010 1 01 0M

Z8018xFamily MPU User Manual268UM005003-0703 LDIRLDDR(If BCR¹0)MC1 T1T2T3 1st Op Code Address1st Op Code010 1 01 0MC2 T1T2T3

Z8018xFamily MPU User Manual UM005003-0703269OUT (m),AMC1 T1T2T3 1st Op Code Address1st Op Code010 1 01 0MC2 T1T2T3 1

Z8018xFamily MPU User Manual270UM005003-0703 OTIM**OTDM**MC1 T1T2T3 1st Op Code Address1st Op Code010 1 01 0MC2 T1T2T3 2nd O

Z8018xFamily MPU User Manual UM005003-0703271OTIMR**OTDMR**(if Br= 0)MC1 T1T2T3 1st Op Code Address1st Op Code010 1 0

Z8018xFamily MPU User Manual272UM005003-0703 OTIROTDR(if Br=0)MC1 T1T2T3 1st Op Code Address1st Op Code010 1 01 0MC2 T1T2T3

Z8018xFamily MPU User Manual UM005003-0703273PUSH IXPUSH IYMC1 T1T2T3 1st Op Code Address1st Op Code010 1 01 0MC2 T1T

Z8018xFamily MPU User Manual14UM005003-0703 Central Processing UnitThe CPU is microcoded to provide a core that is object co

Z8018xFamily MPU User Manual274UM005003-0703 RETI (Z)MC1 T1T2T3 1st Op Code Address1st Op Code010 1 0*5110MC2 T1T2T3 2nd Op

Z8018xFamily MPU User Manual UM005003-0703275RLC (HL)RL (HL)RRC (HL)RR (HL)SLA (HL)SRA (HL)SRL (HL)MC1 T1T2T3 1st Op

Z8018xFamily MPU User Manual276UM005003-0703 RST vMC1 T1T2T3 1st Op Code Address1st Op Code010 1 01 0MC2~MC3TiTi * Z 1 1 1 1

Z8018xFamily MPU User Manual UM005003-0703277SET b, (IX+d)SET b, (IY+d)RES b, (IX+d)RES b, (IY+d)MC1 T1T2T3 1st Op Co

Z8018xFamily MPU User Manual278UM005003-0703 TST g**MC1 T1T2T3 1st Op Code Address1st Op Code010 1 01 0MC2 T1T2T3 2nd Op Cod

Z8018xFamily MPU User Manual UM005003-0703279INTERRUPTSTable 52. Interrupts InstructionMachine Cycle States Address

Z8018xFamily MPU User Manual280UM005003-0703 INT0 Mode 2MC1 T1T2TWTWT3NextOp CodeAddress (PC)Vector111 0010MC2Ti * Z 111 111

Z8018xFamily MPU User Manual281 UM005003-0703Operating Modes SummaryREQUEST ACCEPTANCES IN EACH OPERATING MODETabl

Z8018xFamily MPU User Manual282UM005003-0703 REQUEST PRIORITYThe Z80180 features three types of requests..Type 1, Type 2, an

Z8018xFamily MPU User Manual UM005003-0703283Note: If Bus Request and Refresh Request occur simultaneously, Bus Reque

Z8018xFamily MPU User Manual UM005003-0703iiiMANUAL OBJECTIVESThis user manual describes the features of the Z8018x MPU

Z8018xFamily MPU User Manual UM005003-070315OPERATION MODESThe Z8X180 can be configured to operate like the Hitachi H

Z8018xFamily MPU User Manual284UM005003-0703 Figure 94. Operation Mode Transition* 1. NORMAL: CPU executes instructions norm

Z8018xFamily MPU User Manual UM005003-0703285–DREQ0, DREQ1 = 1 memory to/from (memory mapped) I/O DMA transfer– BCR0,

Z8018xFamily MPU User Manual286UM005003-0703

Z8018xFamily MPU User Manual287 UM005003-0703Status SignalsPIN OUTPUTS IN EACH OPERATING MODETable 55 describes pi

Z8018xFamily MPU User Manual288UM005003-0703 •1 : High•0 : Low•A : Programmable•Z : High Impedance•IN : Input•OUT : Output•* :

Z8018xFamily MPU User Manual UM005003-0703289Table 56. Pin Status During RESET and LOW POWER OPERATION Modes Symbol

Z8018xFamily MPU User Manual290UM005003-0703 CKA0(External Clock Mode)Z IN (A) IN (N) IN (N)DREQ0Z IN (N) IN (A) IN (N)TXA1 —

Z8018xFamily MPU User Manual UM005003-0703291•1: HIGH 0: LOW A: Programmable Z: High Impedance•IN (A): Input (Active)

Z8018xFamily MPU User Manual292UM005003-0703

Z8018xFamily MPU User Manual293 UM005003-0703I/O RegistersINTERNAL I/O REGISTERSBy programming IOA7 and IOA6 as th

Z8018xFamily MPU User Manual16UM005003-0703 Figure 6. M1 Temporary Enable TimingM1TE (M1 Temporary Enable): This bit control

Z8018xFamily MPU User Manual294UM005003-0703 ASCI Control Register B Channel 0: CNTLB0 0 2ASCI Control Register B Channel 1:CN

Z8018xFamily MPU User Manual UM005003-0703295ASCI Status Channel 0: STAT0 0 4ASCI Status Channel 1: STAT1 0 5Tabl

Z8018xFamily MPU User Manual296UM005003-0703 ASCI Transmit Data Register Channel 0:ASCI Transmit Data Register Channel 1:ASCI

Z8018xFamily MPU User Manual UM005003-0703297CSI/O Transmit/Receive Data Register: Timer Data Register Channel 0L:Tim

Z8018xFamily MPU User Manual298UM005003-0703 Timer Data Register Channel 1L:Timer Data Register Channel 1H:Timer Reload Regist

Z8018xFamily MPU User Manual UM005003-0703299DMA Memory Address Register Channel 1B:DMA I/O Address Register Channel

Z8018xFamily MPU User Manual300UM005003-0703 MMU Common Base Register: MMU Bank Base Register MMU Common/Bank RegisterOperatio

Z8018xFamily MPU User Manual UM005003-0703301DMA/WAIT Control Register: DCNTL 3 2Table 57. Internal I/O Registers (C

Z8018xFamily MPU User Manual302UM005003-0703 Interrupt Vector Low Register INT/TRAP Control RegisterRefresh Control Register:I

Z8018xFamily MPU User Manual UM005003-0703303ORDERING INFORMATIONCodes•PackageP = Plastic DipV = Plastic Chip Carrier

Z8018xFamily MPU User Manual UM005003-070317Figure 7. I/O Read and Write Cycles with IOC = 1 Timing DiagramWhen IOC i

Z8018xFamily MPU User Manual304UM005003-0703

Z8018xFamily MPU User ManualUM005003-0703305AAC characteristics 197Address generation, physical 64Address mapI/O 44I/O address translation 57Logical e

Z8018xFamily MPU User ManualUM005003-0703306CSI/OBaud rate selection 150Block diagram 146Control/Status register 147, 150, 159, 160, 161, 172External

Z8018xFamily MPU User ManualUM005003-0703307cles) 167Timing diagram (SLEEP and SYSTEM STOP modes) 168Extended addressing 182External clock rise and fa

Z8018xFamily MPU User ManualUM005003-0703308Memory and I/O Wait state insertion 29Memory management unit (MMU) 13Memory to ASCI 109Memory to memory 10

Z8018xFamily MPU User ManualUM005003-0703309CSI/O control/status 147, 150, 159, 160, 161, 172Direct bit field definitions 181DMA mode (DMODE) 97DMA st

Z8018xFamily MPU User ManualUM005003-0703310DMA TEND0 output 108E clock (memory and I/O R/W cycles) 201E clock (R/W and INTACK cycles) 167E clock (SLE

Z8018xFamily MPU User Manual18UM005003-0703 The user must program the Operation Mode Control Register before the first I/O

Z8018xFamily MPU User Manual UM005003-070319The Op Code on the data bus is latched at the rising edge of T3 and the b

Z8018xFamily MPU User Manual20UM005003-0703 Figure 10. Op Code Fetch (with Wait State) Timing DiagramOperand and Data Read/W

Z8018xFamily MPU User Manual UM005003-070321Wait States (TW) are inserted as previously described for Op Code fetch c

Z8018xFamily MPU User Manual22UM005003-0703 Figure 12. Memory Read/Write (with Wait State) Timing DiagramI/O Read/Write Timi

Z8018xFamily MPU User Manual UM005003-070323Figure 13. I/O Read/Write Timing DiagramBasic Instruction TimingAn instru

Z8018xFamily MPU User Manual24UM005003-0703 Figure 14. Instruction Timing DiagramThis instruction moves the contents of a CP

Z8018xFamily MPU User ManualUM005003-0703 ivSectionsZ8018X MPU OperationPresents features, a general description, pins descr

Z8018xFamily MPU User Manual UM005003-070325The external bus is IDLE while the CPU computes the effective address. Fi

Z8018xFamily MPU User Manual26UM005003-0703 When the bus is released, the address (A0–A19), data (D0–D7), and control (MREQ,

Z8018xFamily MPU User Manual UM005003-070327Figure 17. Bus Exchange Timing During CPU Internal OperationWait State Ge

Z8018xFamily MPU User Manual28UM005003-0703 externally synchronizing WAIT input transitions with the rising edge of the syst

Z8018xFamily MPU User Manual UM005003-070329Figure 19. Memory and I/O Wait State Insertion (DCNTL – DMA/Wait Cont

Z8018xFamily MPU User Manual30UM005003-0703 inserted depending on the programmed value in IWI1 and IWI0. Refer to Table 4.WA

Z8018xFamily MPU User Manual UM005003-070331Also, the WAIT input is ignored during RESET. For example, if RESET is de

Z8018xFamily MPU User Manual32UM005003-0703 •The HALT output pin is asserted Low•The external bus activity consists of repea

Z8018xFamily MPU User Manual UM005003-070333.Figure 20. HALT Timing DiagramSLEEP ModeSLEEP mode is entered by executi

Z8018xFamily MPU User Manual34UM005003-0703 •Data Bus, 3-stateSLEEP mode is exited in one of two ways as described below.•RE

Z8018xFamily MPU User ManualUM005003-0703vTable of ContentsZ80180, Z8S180, Z8L180 MPU Operation . . . . . . . . . . . . . . . . . . . .1Features . .

Z8018xFamily MPU User Manual UM005003-070335Figure 21. SLEEP Timing DiagramIOSTOP ModeIOSTOP mode is entered by setti

Z8018xFamily MPU User Manual36UM005003-0703 Low Power Modes (Z8S180/Z8L180 only)The following section is a detailed descript

Z8018xFamily MPU User Manual UM005003-070337STANDBY ModeThe Z8S180/Z8L180 is designed to save power. Two low-power pr

Z8018xFamily MPU User Manual38UM005003-0703 1. Set bits 6 and 3 to 1 and 0, respectively.2. Set the I/O STOP bits (bit 5 of

Z8018xFamily MPU User Manual UM005003-070339If the BREXT bit of the CPU Control Register (CCR) is cleared, asserting

Z8018xFamily MPU User Manual40UM005003-0703 If the Global Interrupt Enable Flag IEF1 is set to 1, and if an interrupt source

Z8018xFamily MPU User Manual UM005003-070341except that the 217 bit wake-up timer is bypassed. All control signals ar

Z8018xFamily MPU User Manual42UM005003-0703 To avoid address conflicts with external I/O, the Z8X180 internal I/O addresses

Z8018xFamily MPU User Manual UM005003-070343Figure 22. I/O Address RelocationInternal I/O Registers Address MapThe in

Z8018xFamily MPU User Manual44UM005003-0703 address to 0. These instructions are IN0, OUT0, OTIM, OTIMR, OTDM, OTDMR and TST

Z8018xFamily MPU User ManualUM005003-0703viBaud Rate Generator(Z8S180/Z8L180-Class Processors Only) . . . . . . . . . . . . . . . 143Clocked Serial

Z8018xFamily MPU User Manual UM005003-070345Timer Data Register Ch 0 L TMDR0L XX001100 0CH 159Data Register Ch 0 H TM

Z8018xFamily MPU User Manual46UM005003-0703 DMA DMA Source Address Register Ch 0L SAR0L XX100000 20H 93DMA Source Address Re

Z8018xFamily MPU User Manual UM005003-070347INT IL Register (Interrupt Vector Low Register)IL XX110011 33H 67INT/TRAP

Z8018xFamily MPU User Manual48UM005003-0703 Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only) Register Mnemonic

Z8018xFamily MPU User Manual UM005003-070349Timer Data Register Ch 0 L TMDR0L XX001100 0CH 159Data Register Ch 0 H TM

Z8018xFamily MPU User Manual50UM005003-0703 DMA DMA Source Address Register Ch 0L SAR0L XX100000 20H 93DMA Source Address Re

Z8018xFamily MPU User Manual UM005003-070351INT IL Register (Interrupt Vector Low Register)IL XX110011 33H 67INT/TRAP

Z8018xFamily MPU User Manual52UM005003-0703 Clock Multiplier Register (CMR: 1EH) (Z8S180/L180-Class Processors Only)Bit 7 6

Z8018xFamily MPU User Manual UM005003-070353CPU Control Register (CCR: 1FH) (Z8S180/L180-Class Processors Only)Bit 76

Z8018xFamily MPU User Manual54UM005003-0703 Memory Management Unit (MMU)The Z8X180 features an on-chip MMU which performs th

Z8018xFamily MPU User ManualUM005003-0703viiFlag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Z8018xFamily MPU User Manual UM005003-070355Figure 23. Logical Address Mapping ExamplesLogical to Physical Address Tr

Z8018xFamily MPU User Manual56UM005003-0703 Figure 24. Physical Address TransitionMMU Block DiagramThe MMU block diagram is

Z8018xFamily MPU User Manual UM005003-070357Whether address translation (Figure 26) takes place depends on the type o

Z8018xFamily MPU User Manual58UM005003-0703 •MMU Common/Bank Area Register (CBAR)•MMU Common Base Register (CBR)•MMU Bank Ba

Z8018xFamily MPU User Manual UM005003-070359Figure 28. Logical Space Configuration (Example)MMU Common/Bank Area Regi

Z8018xFamily MPU User Manual60UM005003-0703 MMU Register DescriptionMMU Common/Bank Area Register (CBAR)CBAR specifies bound

Z8018xFamily MPU User Manual UM005003-070361MMU Common Base Register (CBR)CBR specifies the base address (on 4K bound

Z8018xFamily MPU User Manual62UM005003-0703 MMU Bank Base Register (BBR)BBR specifies the base address (on 4KB boundaries) u

Z8018xFamily MPU User Manual UM005003-070363MMU and RESETDuring RESET, all bits of the CA field of CBAR are set to 1

Z8018xFamily MPU User Manual64UM005003-0703 Figure 29. Physical Address GenerationFigure 30. Physical Address Generation 2Ad

Z8018xFamily MPU User ManualUM005003-0703ixList of FiguresZ80180, Z8S180, Z8L180 MPU Operation . . . . . . . . . . . . . . . . . . . .1Figure 1. 64-

Z8018xFamily MPU User Manual UM005003-070365Packages not containing an A19 pin or situations using TOUT instead of A1

Z8018xFamily MPU User Manual66UM005003-0703 Interrupt Vector Register (I)Mode 2 for INT0 external interrupt, INT1 and INT2 e

Z8018xFamily MPU User Manual UM005003-070367vector table can be relocated on 32 byte boundaries. IL is initialized to

Z8018xFamily MPU User Manual68UM005003-0703 Interrupt Enable Flag 1,2 (IEF1, IEF2)IEF1 controls the overall enabling and dis

Z8018xFamily MPU User Manual UM005003-070369If IEF1 is 0, all maskable interrupts are disabled. IEF1 can be reset to

Z8018xFamily MPU User Manual70UM005003-0703 TRAP InterruptThe Z8X180 generates a non-maskable (not affected by the state of

Z8018xFamily MPU User Manual UM005003-070371stacked PC-1. If UFO is 1, the starting address of the invalid instructio

Z8018xFamily MPU User Manual72UM005003-0703 Figure 33. TRAP Timing - 3rd Op Code UndefinedExternal InterruptsThe Z8X180 feat

Z8018xFamily MPU User Manual UM005003-0703731. DMAC operation is suspended by the clearing of the DME (DMA Main Enabl

Z8018xFamily MPU User Manual74UM005003-0703 Figure 34. NMI UseMain ProgramNMIEF1 0 PCH EF1 PCL PCL PCH NMIInterrupt ServiceP

Z8018xFamily MPU User ManualUM005003-0703xFigure 21. SLEEP Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 35Figure 22. I/O Addre

Z8018xFamily MPU User Manual UM005003-070375Figure 35. NMI TimingINT0 - Maskable Interrupt Level 0The next highest pr

Z8018xFamily MPU User Manual76UM005003-0703 The TRAP interrupt occurs if an invalid instruction is fetched during Mode 0 int

Z8018xFamily MPU User Manual UM005003-070377disabling all maskable interrupts. The interrupt service routine normally

Z8018xFamily MPU User Manual78UM005003-0703 Figure 38. INT0 Mode 1 TimingINT0 Mode 2This method determines the restart addre

Z8018xFamily MPU User Manual UM005003-070379The vector table address is located on 256 byte boundaries in the 64KB lo

Z8018xFamily MPU User Manual80UM005003-0703 Figure 40. INT0 Interrupt Mode 2 Timing DiagramINT1, INT2The operation of extern

Z8018xFamily MPU User Manual UM005003-070381also the interrupt response sequence used for all internal interrupts (ex

Z8018xFamily MPU User Manual82UM005003-0703 individual I/O (PRT, DMAC, CSI/O, ASCI) control register. The lower vector of IN

Z8018xFamily MPU User Manual UM005003-070383Interrupt Sources During RESETInterrupt Vector Register (I)All bits are r

Z8018xFamily MPU User Manual84UM005003-0703 Return from Subroutine (RETI) Instruction SequenceWhen the EDH/4DH sequence is f