Zilog Z8PE002 Manual de usuario descargar pdf (Pagina 18)

Z8PE002

Z8Plus OTP Microcontroller ZiLOG

18 P R E L I M I N A R Y DS008700-Z8X0799

INTERRUPT SOURCES

Table 10 presents the interrupt types, sources, and vectors

available in the Z8Plus. Other processors from the Z8Plus

family may define the interrupts differently.

External Interrupt Sources

External sources can be generated by a transition on the cor-

responding port pin. The interrupt may detect a rising edge,

a falling edge, or both.

Notes: The interrupt sources and trigger conditions are device

dependent. See the device product specification to de-

termine available sources (internal and external), trig-

gering edge options, and exact programming details.

Although interrupts are edge triggered, minimum inter-

rupt request Low and High times must be observed for

proper operation. See the device product specification

for exact timing requirements on external interrupt re-

quests (T

IL, T

IH).

Internal Interrupt Sources

Internal interrupt sources and trigger conditions are device

dependent. On-chip peripherals may set interrupt under var-

ious conditions. Some peripherals always set their corre-

sponding

IREQ bit while others must be specifically con-

figured to do so.

See the device product specification to determine available

sources, triggering edge options, and exact programming

details. For more details on the interrupt sources, refer to

the chapters describing the timers, comparators, I/O ports,

and other peripherals.

Interrupt Mask Register (IMASK) Initialization

The IMASK register individually or globally enables or dis-

ables the interrupts (Table 11). When bits

0 through 5 are

set to

1, the corresponding interrupt requests are enabled.

Bit

7 is the master enable bit and must be set before any of

the individual interrupt requests can be recognized. Reset-

ting bit

7 disables all the interrupt requests. Bit 7 is set and

reset by the

EI and DI instructions. It is automatically set to

0 during an interrupt service routine and set to 1 following

the execution of an Interrupt Return (

IRET) instruction. The

IMASK registers are reset to 00h, disabling all interrupts.

Notes: It is not good programming practice to directly assign a

value to the master enable bit. A value change should

always be accomplished by issuing the EI and DI in-

structions.

Care should be taken not to set or clear IMASK bits

while the master enable is set.

Table 10. Interrupt Types, Sources, and Vectors

Name Sources Vector Location

Comments Fixed Priority

IREQ

Timer0 Time-out 2,3 Internal 1 (Highest)

IREQ

PB4 High-to-Low

Transition

4,5 External (PB4), Edge

Triggered

IREQ

Timer1 Time-out 6,7 Internal 3

IREQ

PB2 High-to-Low

Transition

8,9 External (PB2), Edge

Triggered

IREQ

PB4 Low-to-High

Transition

A,B External (PB4), Edge

Triggered

IREQ

Timer2 Time-out C,D Internal 6 (Lowest)

IREQ

–IREQ

Reserved Reserved for future

expansion

1 2 ... 13 14 15 16 17 18 19 20 21 22 23 ... 47 48

Comentarios a estos manuales

Sin comentarios

Zilog Z8PE002 Manual de usuario Pagina 18

Comentarios a estos manuales

Relacionado con productos y manuales para Sensores Zilog Z8PE002