Zilog Z16C30 Manual de usuario

ZiLOG Worldwide Headquarters • 910 E. Hamilton Avenue • Campbell, CA 95008Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.comZ16C30USCUser’s M

Z16C30 USC®USER'S MANUALviZILOGUM97USC0100FIGURE TITLES PAGEChapter 1Figure 1-1. USC Logic Symbol ...

5-33Z16C30 USC®USER'S MANUALZILOGUM97USC0100TCLRNon-ZeroDetectEnable TCC(FromCommand-DrivenLogic)TxFIFOLDEOF/EOM0001DetectCounter (TCCR)LDDN(SeeT

5-34Z16C30 USC®USER'S MANUALUM97USC0100ZILOG5.19.1 The Character Counters (Continued)RCLRNon-ZeroDetectEnable TCCCounterLDON(SeeText)Rx CharClkD

5-35Z16C30 USC®USER'S MANUALZILOGUM97USC0100On the Receive side, software can’t directly read the RCC(except perhaps by using test modes that are

5-36Z16C30 USC®USER'S MANUALUM97USC0100ZILOG5.19 DMA SUPPORT FEATURES (Continued)If software has enabled the RCC, and a frame or messageends whe

5-37Z16C30 USC®USER'S MANUALZILOGUM97USC010014 13 12 11 10 9 8 7 6 5 4 3 2 1 015Reserved(0)Wait4RxTrigRxStatBlkAsync:TxShaveLSync:TxPreL Sync:TxP

5-38Z16C30 USC®USER'S MANUALUM97USC0100ZILOG5.19.4 Receive Status BlocksA USC Receiver sets the RxBound bit in the RxFIFO toindicate the end of

5-39Z16C30 USC®USER'S MANUALZILOGUM97USC0100The only trouble with the 32-bit RSB option is that softwarehas to know how long each received frame

5-40Z16C30 USC®USER'S MANUALUM97USC0100ZILOG5.20 COMMANDSCommands are encoded values that software writes to aregister field to change the state

5-41Z16C30 USC®USER'S MANUALZILOGUM97USC010014 13 12 11 10 9 8 7 6 5 4 3 2 1 015RTCmdRTResetRTModeChanLoadB//WRegAddrU//LFigure 5-19. The Channe

5-42Z16C30 USC®USER'S MANUALUM97USC0100ZILOG5.20 COMMANDS (Continued)Enter Hunt Mode (RCmd:=0011): this command forcesthe Receiver into “Hunt Mo

Z16C30 USC®USER'S MANUALviiZILOGUM97USC0100FIGURE TITLES PAGEChapter 5Figure 5-1. Asynchronous Data ...

5-43Z16C30 USC®USER'S MANUALZILOGUM97USC0100Select RICRHi=/INT Level (RCmd:=0110): this commandconditions a channel so that subsequent accesses t

5-44Z16C30 USC®USER'S MANUALUM97USC0100ZILOG5.20 COMMANDS (Continued)Trigger Channel Load DMA (RTCmd:=00100): Chapter 7will describe how this co

5-45Z16C30 USC®USER'S MANUALZILOGUM97USC01005.22 THE DATA REGISTERS AND THE FIFOSWhen the RxFIFO contains received characters, softwarecan read

5-46Z16C30 USC®USER'S MANUALUM97USC0100ZILOG5.22.4 DMA and Interrupt Request LevelsThe USC channels continually compare the contents of theFill

5-47Z16C30 USC®USER'S MANUALZILOGUM97USC01005.23 HANDLING OVERRUNS AND UNDERRUNSIn general, both the Tx Underrun condition in the TCSR andthe Rx

5-48Z16C30 USC®USER'S MANUALUM97USC0100ZILOG5.23 HANDLING OVERRUNS AND UNDERRUNS (Continued)3. On an USC manufactured after June of 1993, write

5-49Z16C30 USC®USER'S MANUALZILOGUM97USC01005.24 BETWEEN FRAMES, MESSAGES, OR CHARACTERS5.24.1 Synchronous TransmissionWhen software issues a “

5-50Z16C30 USC®USER'S MANUALUM97USC0100ZILOG5.24 BETWEEN FRAMES, MESSAGES, OR CHARACTERS (Continued)In sync modes, once the conditions to start

5-51Z16C30 USC®USER'S MANUALZILOGUM97USC01005.24.3 Synchronous ReceptionBetween the end of one message or frame and the start ofthe next, the Re

5-52Z16C30 USC®USER'S MANUALUM97USC0100ZILOGZilog’s products are not authorized for use as critical compo-nents in life support devices or system

Z16C30 USC®USER'S MANUALviiiZILOGUM97USC0100FIGURE TITLES PAGEChapter 7Figure 7-1. An Interrupt Daisy Chain ...

6-1Z16C30 USC®USER'S MANUALZILOGUM97USC01006.1 INTRODUCTIONUSER’s MANUALCHAPTER 6DIRECT MEMORY ACCESS (DMA)INTERFACINGChapter 5 described many o

6-2Z16C30 USC®USER'S MANUALUM97USC0100ZILOG6.2 FLYBY VS. FLOWTHROUGH DMA OPERATION (Continued)DMACMemory DevicedataREQDMACMemory DevicedataREQAd

6-3Z16C30 USC®USER'S MANUALZILOGUM97USC0100DMACMemory DevicedataREQDMACMemory DevicedataREQAddressData Register in DeviceMemory Location/RDDatafr

6-4Z16C30 USC®USER'S MANUALUM97USC0100ZILOG6.2 FLYBY VS. FLOWTHROUGH DMA OPERATION (Continued)Figure 6-3. Flyby DMA Transfer, Memory to Periphe

6-5Z16C30 USC®USER'S MANUALZILOGUM97USC0100Figure 6-4. *Flyby DMA Transfer, Peripheral Device to MemoryDMACMemory DeviceREQAddressMemory Locatio

6-6Z16C30 USC®USER'S MANUALUM97USC0100ZILOG6.2 FLYBY VS. FLOWTHROUGH DMA OPERATION (Continued)Figures 6-3 and 6-4 illustrate flyby (single-cycle

6-7Z16C30 USC®USER'S MANUALZILOGUM97USC0100“Forcing out a frame” in D1. above applies only in HDLC/SDLC, HDLC/SDLC Loop, 802.3, or Transparent Bi

6-8Z16C30 USC®USER'S MANUALUM97USC0100ZILOG6.3.1 Programming the DMA Request Levels (Continued)Code that writes or reads a DMA Request threshold

6-9Z16C30 USC®USER'S MANUALZILOGUM97USC0100Zilog’s products are not authorized for use as critical compo-nents in life support devices or systems

7-1Z16C30 USC®USER'S MANUALZILOGUM97USC01007.1 INTRODUCTIONUSER’s MANUALCHAPTER 7INTERRUPTSThe interrupt subsystem of the USC derives from Zilog

Z16C30 USC®USER'S MANUALixZILOGUM97USC0100TABLE TITLES PAGEChapter 1Table 1-1. Bus Interfacing Features of the USC ...

7-2Z16C30 USC®USER'S MANUALUM97USC0100ZILOG7.2 INTERRUPT ACKNOWLEDGE DAISY-CHAINS (Continued)7.3 EXTERNAL INTERRUPT CONTROL LOGICThere are two

7-3Z16C30 USC®USER'S MANUALZILOGUM97USC01007.4 USING /RXREQ AND /TXREQ AS INTERRUPT REQUESTSWhen an external DMA controller isn’t used to handle

7-4Z16C30 USC®USER'S MANUALUM97USC0100ZILOG7.5 INTERRUPT TYPES AND SOURCESInternally, the USC uses a daisy-chaining scheme muchlike that describ

7-5Z16C30 USC®USER'S MANUALZILOGUM97USC0100Figure 7-3. USC Interrupt Types and SourcesExited HuntIAIdle ReceivedIABreak/AbortIARx BoundaryIAAbor

7-6Z16C30 USC®USER'S MANUALUM97USC0100ZILOG7.6 INTERNAL INTERRUPT OPERATIONFigure 7-4 presents a model of the typical internal structureof the i

7-7Z16C30 USC®USER'S MANUALZILOGUM97USC0100/tIUS/IACKcyTo IEO orNext-Lower-PriorityTypetIEADnbWRREGbResetDQ/QCLRFrom OtherTypes/INTMIEFrom IEI pi

7-8Z16C30 USC®USER'S MANUALUM97USC0100ZILOG7.7 DETAILS OF THE MODELThe IA and IE bits appear near the left side of Figure 7-4,as D-type flip-flo

7-9Z16C30 USC®USER'S MANUALZILOGUM97USC01007.8 INTERRUPT OPTION IN THE BCROne bit in the Bus Configuration Register (BCR) affects theinterrupt s

7-10Z16C30 USC®USER'S MANUALUM97USC0100ZILOG7.9 INTERRUPT ACKNOWLEDGE CYCLES (Continued)AD15-AD0(not used) vector/SITACK/ASIEOIEI/DS OR /RD/WAIT

7-11Z16C30 USC®USER'S MANUALZILOGUM97USC0100Figure 7-6 shows an interrupt acknowledge cycle that’ssignalled by /SITACK, on a bus with separate ad

1-1Z16C30 USC®USER'S MANUALZILOGUM97USC01001.1 INTRODUCTIONUSER’s MANUALCHAPTER 1INTRODUCTIONThe Universal Serial Controller (USC®) is the next-

7-12Z16C30 USC®USER'S MANUALUM97USC0100ZILOG7.9 INTERRUPT ACKNOWLEDGE CYCLES (Continued)Figure 7-7 shows the kind of interrupt acknowledge cycle

7-13Z16C30 USC®USER'S MANUALZILOGUM97USC0100Figure 7-8 shows the kind of interrupt acknowledge cyclethat the USC expects when /PITACK goes low an

7-14Z16C30 USC®USER'S MANUALUM97USC0100ZILOG7.10 INTERRUPT ACKNOWLEDGE VS. READ CYCLESInterrupt Acknowledge cycles are similar to the cycles tha

7-15Z16C30 USC®USER'S MANUALZILOGUM97USC0100Abort/PE If the IA bit for this source is 1, the interruptlogic sets the RS IP bit when software orth

7-16Z16C30 USC®USER'S MANUALUM97USC0100ZILOG7.11.2 Receive Data Interrupts (Continued)To program the Receive Data Interrupt Request Level, first

7-17Z16C30 USC®USER'S MANUALZILOGUM97USC0100Start: Interrupt withVector = "Rx Data"CT=0?Clear the RD IP bit(write 9016to DCCR7-0)YesRe

7-18Z16C30 USC®USER'S MANUALUM97USC0100ZILOG7.11.2 Receive Data Interrupts (Continued)7.11.3 Transmit Status Interrupt Sourcesand IA BitsThe in

7-19Z16C30 USC®USER'S MANUALZILOGUM97USC0100the corresponding bit in the Transmit Command/StatusRegister (TCSR) goes from 0 to 1. If an IA bit is

7-20Z16C30 USC®USER'S MANUALUM97USC0100ZILOG7.11.5 I/O Pin Interrupt Sources and IA BitsThe interrupt logic can set the I/O Pin IP bit in respon

7-21Z16C30 USC®USER'S MANUALZILOGUM97USC01007.12 INTERRUPT PENDING AND UNDER SERVICE BITSSoftware can read, set, and clear the Interrupt Pending

1-2Z16C30 USC®USER'S MANUALUM97USC0100ZILOG1.3 LOGIC SYMBOLZ16C30USC/RESET/CSA//BD//C/AS/RxCA,B/TxCA,BRxDA,B/CTSA,B/DCDA,BAD15-AD0/WAIT//RDY/INT

7-22Z16C30 USC®USER'S MANUALUM97USC0100ZILOG7.14 CHANNEL INTERRUPT OPTIONSFigure 7-17 shows that the MSByte of the Interrupt ControlRegister (IC

7-23Z16C30 USC®USER'S MANUALZILOGUM97USC0100The Vector Includes Status field (VIS; ICR12-9) controlswhether the vector, that the channel returns

7-24Z16C30 USC®USER'S MANUALUM97USC0100ZILOG7.15 INTERRUPT VECTORS (Continued)7.16 SOFTWARE REQUIREMENTS14 13 12 11 10 9 8 7 6 5 4 3 2 1 015Int

7-25Z16C30 USC®USER'S MANUALZILOGUM97USC01007.16.3 Handling a TypeThe process of handling a single type of interrupt is thesame regardless of wh

7-26Z16C30 USC®USER'S MANUALUM97USC0100ZILOGc. The hardware automatically tags the character thatcorresponds to decrementing the TCC from 1 to 0.

7-27Z16C30 USC®USER'S MANUALZILOGUM97USC0100Not using the TCC:a. Software doesn’t need to do anything special to theUSC at the start of a frame,

8-1Z16C30 USC®USER'S MANUALZILOGUM97USC01008.1 INTRODUCTIONUSER’s MANUALCHAPTER 8SOFTWARE SUMMARYThis chapter includes a bit by bit description

8-2Z16C30 USC®USER'S MANUALZILOGUM97USC01008.3 PROGRAMMING ORDERUSC® family members aren’t as particular about the orderin which software progra

8-3Z16C30 USC®USER'S MANUALZILOGUM97USC01008.5 DETERMINING THE DEVICE REVISION LEVELZilog makes every effort to improve devices like the 16C30wh

8-4Z16C30 USC®USER'S MANUALZILOGUM97USC01008.6.2 COMMON SOFTWARE PROBLEMS (Continued)S2. WordStatus problemsIn general, software wants to progr

1-3Z16C30 USC®USER'S MANUALZILOGUM97USC01001.4 PACKAGINGZ16C30 USC(Top View)1011121314151617181920212223242526605958575655545352515049484746454

8-5Z16C30 USC®USER'S MANUALZILOGUM97USC0100S7. Interrupt handlingA new section at the end of Chapter 7 gives specificrequirements for each type

8-6Z16C30 USC®USER'S MANUALZILOGUM97USC01008.7 TEST MODESThe USC includes a facility intended for Zilog’s devicetesting, that gives software acc

8-7Z16C30 USC®USER'S MANUALZILOGUM97USC0100D7 D6 D5 D4 D3 D2 D1 D0D15 D14 D13 D12 D11 D10 D9 D80RxC Pad OutputCTR0 Enable/Rx ClockCTR0 Clock/Tx C

8-8Z16C30 USC®USER'S MANUALZILOGUM97USC01008.7 TEST MODES (Continued)D7 D6 D5 D4 D3 D2 D1 D0D15 D14 D13 D12 D11 D10 D9 D80TxC PadRx Sync/Rx Cloc

8-9Z16C30 USC®USER'S MANUALZILOGUM97USC0100D7 D6 D5 D4 D3 D2 D1 D0D15 D14 D13 D12 D11 D10 D9 D8BRG0 ZC Status LatchBRG1 ZC Status LatchDPLL Sync

8-10Z16C30 USC®USER'S MANUALZILOGUM97USC01008.8 REGISTER REFERENCEThe following pages include all of the fields in all of theregisters in one of

8-11Z16C30 USC®USER'S MANUALZILOGUM97USC010014 13 12 11 10 9 8 7 6 5 4 3 2 1 015Reserved (Must be zero)Bus Configuration Register (BCR) No Addres

8-12Z16C30 USC®USER'S MANUALZILOGUM97USC010014 13 12 11 10 9 8 7 6 5 4 3 2 1 015RTCmdChannel Command/Address Register (CCAR) Register Address 0

8-13Z16C30 USC®USER'S MANUALZILOGUM97USC010014 13 12 11 10 9 8 7 6 5 4 3 2 1 015ClearRCCFChannel Command/Status Register (CCSR) Register Address

8-14Z16C30 USC®USER'S MANUALZILOGUM97USC010014 13 12 11 10 9 8 7 6 5 4 3 2 1 015Wait4Tx TrigChannel Control Register (CCR) Register Address 0 b 0

1-4Z16C30 USC®USER'S MANUALUM97USC0100ZILOG1.5 OVERVIEW OF THE USC AND THIS MANUALThe following descriptions and Tables should be helpful ininit

8-15Z16C30 USC®USER'S MANUALZILOGUM97USC010014 13 12 11 10 9 8 7 6 5 4 3 2 1 015TxSubModeChannel Mode Register (CMR) Register Address 0 b 00001Tx

8-16Z16C30 USC®USER'S MANUALZILOGUM97USC0100Bit(s)Field/BitNameConditions/ContextDescriptionRWStatusRef Chapter: SectionChannel Mode Register (CM

8-17Z16C30 USC®USER'S MANUALZILOGUM97USC0100Bit(s)Field/BitNameConditions/ContextDescriptionRWStatusRef Chapter: SectionCMR11-8Channel Mode Regis

8-18Z16C30 USC®USER'S MANUALZILOGUM97USC010014 13 12 11 10 9 8 7 6 5 4 3 2 1 015BRG0SrcClock Mode Control Register (CMCR) Register Address 0 b 0

8-19Z16C30 USC®USER'S MANUALZILOGUM97USC010014 13 12 11 10 9 8 7 6 5 4 3 2 1 015IOPIUSDaisy Chain Control Register (DCCR) Register Address 0 b 01

8-20Z16C30 USC®USER'S MANUALZILOGUM97USC010014 13 12 11 10 9 8 7 6 5 4 3 2 1 015CTR0DivHardware Configuration Register (HCR) Register Address 0

8-21Z16C30 USC®USER'S MANUALZILOGUM97USC010014 13 12 11 10 9 8 7 6 5 4 3 2 1 015CTSModeInput/Output Control Register (IOCR) Register Address 0 b

8-22Z16C30 USC®USER'S MANUALZILOGUM97USC010014 13 12 11 10 9 8 7 6 5 4 3 2 1 015MIEInterrupt Control Register (ICR) Register Address 0 0 b 01100B

8-23Z16C30 USC®USER'S MANUALZILOGUM97USC010014 13 12 11 10 9 8 7 6 5 4 3 2 1 015Interrupt Vector7-4 (RO)Interrupt Vector Register (IVR) Register

8-24Z16C30 USC®USER'S MANUALZILOGUM97USC010014 13 12 11 10 9 8 7 6 5 4 3 2 1 015RxCL/UMiscellaneous Interrupt Status Register (MISR) Register Add

1-5Z16C30 USC®USER'S MANUALZILOGUM97USC0100Table 1-1 Bus Interfacing Features of the USC (Chapter 2)Multiplexed or Separate Address and Data Bus

8-25Z16C30 USC®USER'S MANUALZILOGUM97USC0100Bit(s)Field/BitNameConditions/ContextDescriptionRWStatusRef Chapter: SectionRCCR15-014 13 12 11 10 9

8-26Z16C30 USC®USER'S MANUALZILOGUM97USC010014 13 12 11 10 9 8 7 6 5 4 3 2 1 015Rcmd (WO)Receive Command/Status Register (RCSR) Register Address

8-27Z16C30 USC®USER'S MANUALZILOGUM97USC010014 13 12 11 10 9 8 7 6 5 4 3 2 1 015Starting value for Receive Character CounterReceive Count Limit R

8-28Z16C30 USC®USER'S MANUALZILOGUM97USC0100"RxFIFO Status" if last RCSR15-12 command 4-7 was 5"Rx Int level" if last RCSR15

8-29Z16C30 USC®USER'S MANUALZILOGUM97USC0100RxDecodeReceive Mode Register (RMR) Register Address 0 b 10001RxParEnabRxCRCTypeRxCRCStartRxCRCEnabQA

8-30Z16C30 USC®USER'S MANUALZILOGUM97USC010014 13 12 11 10 9 8 7 6 5 4 3 2 1 015RxCDnIAStatus Interrupt Control Register (SICR) Register Address

8-31Z16C30 USC®USER'S MANUALZILOGUM97USC010014 13 12 11 10 9 8 7 6 5 4 3 2 1 015Test Register selected by TMCR4-0Test Mode Data Register (TMDR) R

8-32Z16C30 USC®USER'S MANUALZILOGUM97USC010014 13 12 11 10 9 8 7 6 5 4 3 2 1 015Current value of Transmit Character CounterTransmit Character Cou

8-33Z16C30 USC®USER'S MANUALZILOGUM97USC010014 13 12 11 10 9 8 7 6 5 4 3 2 1 015TCmdTransmit Command/Status Register (TCSR) Register Address 0 b

8-34Z16C30 USC®USER'S MANUALZILOGUM97USC010014 13 12 11 10 9 8 7 6 5 4 3 2 1 015Transmit character: write only using 16-bit operationTransmit Dat

1-6Z16C30 USC®USER'S MANUALUM97USC0100ZILOG1.5.6 Software Summary (Continued)Table 1-2. Serial Interfacing Features of the USC (Chapter 4)Clock

8-35Z16C30 USC®USER'S MANUALZILOGUM97USC0100"TxFIFO Status" if last TCSR15-12 command 4-7 was 5"Tx/Int level" if last TCSR15-

8-36Z16C30 USC®USER'S MANUALZILOGUM97USC010014 13 12 11 10 9 8 7 6 5 4 3 2 1 015TxEncodeTransmit Mode Register (TMR) Register Address 0 b 11001B

8-37Z16C30 USC®USER'S MANUALZILOGUM97USC0100Zilog’s products are not authorized for use as critical compo-nents in life support devices or system

A-1Z16C30 USC®USER'S MANUALZILOGUM97USC0100A.1 INTRODUCTIONUSER’s MANUALAPPENDIX AAPPENDIX CHANGESThis is for the reader of previous USC documen

A-2Z16C30 USC®USER'S MANUALUM97USC0100ZILOGJune 1993 Changes1. HDLC/SDLC Abort status can be queued with re-ceived characters (p. 5-33).2. Receiv

B-1Z16C30 USC®USER'S MANUALZILOGUM97USC0100USER’s MANUALAPPENDIX BQUESTIONS & ANSWERSUSC FAMILY QUESTIONS AND ANSWERSThe following is a compi

B-2Z16C30 USC®USER'S MANUALUM97USC0100ZILOGGeneral Questions and Answers (Continued)Q: New and old samples of the USC act differently whenprogram

B-3Z16C30 USC®USER'S MANUALZILOGUM97USC01000 of the data bus. Similarly, data to be written to thehigh order byte (D15-8) should be on AD15-8. Re

B-4Z16C30 USC®USER'S MANUALUM97USC0100ZILOGSERIAL & PROTOCOL QUESTIONS AND ANSWERS (Continued)Q: Running asynchronous mode, how do you progra

B-5Z16C30 USC®USER'S MANUALZILOGUM97USC0100Q: With the DPLL, what is the purpose of multiple possi-bilities of divisors?A: The DPLL is used to re

Z16C30USCUM009402-0201This publication is subject to replacement by a later edition. To determine whether a lateredition exists, or to request copies

1-7Z16C30 USC®USER'S MANUALZILOGUM97USC0100Table 1-3. Serial Controller Features of the USCMajor Protocol Categories Chapter 4 begins with a sma

B-6Z16C30 USC®USER'S MANUALUM97USC0100ZILOGSERIAL & PROTOCOL QUESTIONS AND ANSWERS (Continued)Q: Is there a minimum length for HDLC/SDLC fram

B-7Z16C30 USC®USER'S MANUALZILOGUM97USC0100Q: Does the Purge Rx FIFO command clear the ReceiveCharacter Counter?A: No, the Purge Rx FIFO command

B-8Z16C30 USC®USER'S MANUALUM97USC0100ZILOGSERIAL & PROTOCOL QUESTIONS AND ANSWERS (Continued)Q: The Transmit Control Block is being sent as

B-9Z16C30 USC®USER'S MANUALZILOGUM97USC0100Q: When the DMA in the IUSC reads external memory forarray or linked-list table information, does it a

B-10Z16C30 USC®USER'S MANUALUM97USC0100ZILOGDMA QUESTIONS AND ANSWERS (Continued)Q: Since the Receive Status Block is appended to the endof the d

B-11Z16C30 USC®USER'S MANUALZILOGUM97USC0100Q: Are there some rules of thumb to tune the device forperformance problems?A: If you are experiencin

B-12Z16C30 USC®USER'S MANUALUM97USC0100ZILOGINTERRUPT QUESTIONS AND ANSWERSDMA QUESTIONS AND ANSWERS (Continued)Q: Why is the /BIN input sampled

B-13Z16C30 USC®USER'S MANUALZILOGUM97USC0100Q: The IUSC Technical Manual states that /DS and/INTACK should never be active at the same time.Howev

B-14Z16C30 USC®USER'S MANUALUM97USC0100ZILOGZilog’s products are not authorized for use as critical compo-nents in life support devices or system

1-8Z16C30 USC®USER'S MANUALUM97USC0100ZILOGTable 1-4. More Serial Controller Features of the USCTransmit Control Blocks A Transmit DMA channel c

1-9Z16C30 USC®USER'S MANUALZILOGUM97USC0100Table 1-5. DMA Features of the USCFlowthrough or Flyby The USC can be used with DMA controllers in a

1-10Z16C30 USC®USER'S MANUALUM97USC0100ZILOGTable 1-6. Interrupt Features of the USCInterrupt AcknowledgeDaisy Chaining was one of Zilog’s origi

1-11Z16C30 USC®USER'S MANUALZILOGUM97USC0100Serial ClockLogicDPLLCountersBRG0, BRG1TransmitterInterruptControlInterruptControlBusInterfaceReceive

1-12Z16C30 USC®USER'S MANUALUM97USC0100ZILOG1.6 DEVICE STRUCTUREFigure 1-1 shows the basic structure of the USC. The BusInterface module stands

1-13Z16C30 USC®USER'S MANUALZILOGUM97USC01001.7 DOCUMENT STRUCTUREThe Chapters in this manual attempt to provide the first-time reader with a st

2-1Z16C30 USC®USER'S MANUALZILOGUM97USC01002.1 INTRODUCTIONUSER’s MANUALCHAPTER 2BUS INTERFACINGThe USC® can be used in systems with various mic

2-2Z16C30 USC®USER'S MANUALUM97USC0100ZILOG2.2 MULTIPLEXED/NON-MULTIPLEXED OPERATION (Continued)68000D15:D0/ASUSCAD15:AD0/ASVCCFigure 2-3. User

2-3Z16C30 USC®USER'S MANUALZILOGUM97USC01002.3 READ/WRITE DATA STROBESAnother difference among host buses is the way in whichread and write cycl

Z16C30 USC® USER'S MANUALSUPPLEMENTARY INFORMATIONZILOGUM97USC0100Z16C30 USC® USER'S MANUALThank you for your interest in Zilog's high-

2-4Z16C30 USC®USER'S MANUALUM97USC0100ZILOG2.4 BUS WIDTHAnother major difference among host buses is the numberof data bits that can be transfer

2-5Z16C30 USC®USER'S MANUALZILOGUM97USC0100RD* or WR*or DS*WAIT*ACK*ReadyFigure 2-6. A Fast and Slow Cycle, with Three Kinds of Handshaking2.6

2-6Z16C30 USC®USER'S MANUALUM97USC0100ZILOG2.6 PIN DESCRIPTIONS (Continued)R//W. Read/Write control (input, low signifies “write”).R//W and /DS

2-7Z16C30 USC®USER'S MANUALZILOGUM97USC01002.7 PULL-UP RESISTORS AND UNUSED PINSAll unused input pins should be pulled up, either byconnecting t

2-8Z16C30 USC®USER'S MANUALUM97USC0100ZILOG2.8.2 Bits and Fields in the BCR (Continued)16-Bit (BCR2): this bit should be written as 1 when the h

2-9Z16C30 USC®USER'S MANUALZILOGUM97USC0100Whenever it uses CCAR as an indirect address, the USCthereafter clears CCAR6-0 to zero, so that the ne

2-10Z16C30 USC®USER'S MANUALUM97USC0100ZILOG2.9.5 About the Register Address TablesTables 2-1 and 2-2 show the names and addresses of theaddress

2-11Z16C30 USC®USER'S MANUALZILOGUM97USC0100Figure 2-9. USC Register AddressingActivityon /AS afterReset?SEPAD(BCR15)Start: Host Cyclewith /CS

2-12Z16C30 USC®USER'S MANUALUM97USC0100ZILOG2.9 Register Addressing (Continued)Table 2-1. USC Registers, in Address Order

2-13Z16C30 USC®USER'S MANUALZILOGUM97USC0100Table 2-2. USC Registers, in Alphabetical OrderCCAR6-0 Indirect Address Channel AReg

Z16C30 USC® USER'S MANUALSUPPLEMENTARY INFORMATIONUM97USC0100ZILOGDemonstration/Evaluation Boards (Continued)Z16C3001ZCO - This kit contains an a

2-14Z16C30 USC®USER'S MANUALUM97USC0100ZILOG2.9.6 Serial Data Registers TDR and RDRThe RDR and TDR are actually “the read and write sides of”the

2-15Z16C30 USC®USER'S MANUALZILOGUM97USC0100ADnnAddressDataA//B, D//C/CS/SITACK/PITACK,/WR,(/RD OR /DS),DMA Acknowledge signals/ASR//W(Required w

2-16Z16C30 USC®USER'S MANUALUM97USC0100ZILOG2.9.7 Register Read and Write Cycles (Continued)ADnnA//B, D//C/CS/SITACK/PITACK, /RD,(/WR or /DS),DM

2-17Z16C30 USC®USER'S MANUALZILOGUM97USC0100DataADnnA//B, D//C/CS/SITACK/PITACK, /WR, (/RD OR /DS),DMA Acknowledge signalsR//W/DS or /RD/WAIT//RD

2-18Z16C30 USC®USER'S MANUALUM97USC0100ZILOGDataADnnA//B,D//C/CS/SITACK/PITACK,/AS,/RD,(/WR or /DS),DMA Acknowledge signalsR//W/DS or /WR/WAIT//R

3-1Z16C30 USC®USER'S MANUALZILOGUM97USC01003.1 INTRODUCTIONUSER’s MANUALCHAPTER 3A SAMPLE APPLICATIONFigures 3-1 and 3-2 are schematics of a sim

3-2Z16C30 USC®USER'S MANUALUM97USC0100ZILOG3.1 INTRODUCTION (Continued)Figure 3-1. Sample ApplicationUM009402-0201

3-3Z16C30 USC®USER'S MANUALZILOGUM97USC0100Figure 3-2. Serial Interface for Sample ApplicationUM009402-0201

3-4Z16C30 USC®USER'S MANUALUM97USC0100ZILOG3.1 INTRODUCTION (Continued)U7-9 are octal latches that capture the address from the186 and present t

3-5Z16C30 USC®USER'S MANUALZILOGUM97USC0100Zilog’s products are not authorized for use as critical compo-nents in life support devices or systems

Z16C30 USC®USER'S MANUALiZILOGUM97USC0100TABLE OF CONTENTSChapter 1 Introduction1.1 Introduction ...

4-1Z16C30 USC®USER'S MANUALZILOGUM97USC01004.1 INTRODUCTIONUSER’s MANUALCHAPTER 4SERIAL INTERFACINGThe USC® includes several serial interface op

4-2Z16C30 USC®USER'S MANUALUM97USC0100ZILOG4.3 TRANSMIT AND RECEIVE CLOCKINGThe USC’s Receiver and Transmitter logic have separateinternal clock

4-3Z16C30 USC®USER'S MANUALZILOGUM97USC0100CMCR13-12CTR00123MUXQ4Q3Q2Q1Q00123MUXHCR15-14RxCTxCCMCR15-14CTR00123MUXQ4Q3Q2Q1Q00123MUX01MUXHRC13DREF

4-4Z16C30 USC®USER'S MANUALUM97USC0100ZILOG4.3.2 The Baud Rate Generators (Continued)RxCLKSrcCTR1Src14 13 12 11 10 9 8 7 6 5 4 3 2 1 015TxCLKSrc

4-5Z16C30 USC®USER'S MANUALZILOGUM97USC0100The output of either Baud Rate Generator can be used asRxCLK and/or TxCLK. It can be used as the refer

4-6Z16C30 USC®USER'S MANUALUM97USC0100ZILOG4.3.5 Clocking for Asynchronous ModeFor asynchronous reception, transitions on RxCLK don’thave to hav

4-7Z16C30 USC®USER'S MANUALZILOGUM97USC01004.4 DATA FORMATS AND ENCODINGThe USC’s Transmitter and Receiver can handle data inany of the eight fo

4-8Z16C30 USC®USER'S MANUALUM97USC0100ZILOG4.4 DATA FORMATS AND ENCODING (Continued)In NRZI-Mark mode, at the start of each bit cell thetransmit

4-9Z16C30 USC®USER'S MANUALZILOGUM97USC0100In the Bi-phase-Level and Differential Bi-phase-Levelencodings, there is always a transition at the mi

4-10Z16C30 USC®USER'S MANUALUM97USC0100ZILOG4.5 MORE ABOUT THE DPLL (Continued)After software sets up the DPLL, three bits in the ChannelCommand

Z16C30 USC®USER'S MANUALiiZILOGUM97USC0100CHAPTER TITLE AND SUBSECTIONS PAGEChapter 3 A Sample Introduction3.1 Introduction ...

4-11Z16C30 USC®USER'S MANUALZILOGUM97USC0100The RTMode field of the Channel Command/Addressregister (CCAR9-8) controls the relationship between

4-12Z16C30 USC®USER'S MANUALUM97USC0100ZILOG4.7 EDGE DETECTION AND INTERRUPTS (Continued)While an L/U bit is 1, the state of the associated data

4-13Z16C30 USC®USER'S MANUALZILOGUM97USC01004.8 THE /DCD PINThe DCDMode field of the I/O Control Register (IOCR13-12) controls the function of t

4-14Z16C30 USC®USER'S MANUALUM97USC0100ZILOG4.8 THE /DCD PIN (Continued)/DCDRxCLK(/RxC)RxD (Async, 9-BitACV/1553BRxD (Isochronous)RxD (External

4-15Z16C30 USC®USER'S MANUALZILOGUM97USC01004.9 THE /CTS PINThe CTSMode field of the I/O Control Register (IOCR15-14) controls the function of t

4-16Z16C30 USC®USER'S MANUALUM97USC0100ZILOG4.10 THE /RXC AND /TXC PINSFigure 4-1 shows each channel’s options for the function ofits /RxC and /

4-17Z16C30 USC®USER'S MANUALZILOGUM97USC01004.11 THE /RXREQ AND /TXREQ PINSThe RxRMode and TxRMode fields of the I/O ControlRegister (IOCR9-8 a

4-18Z16C30 USC®USER'S MANUALUM97USC0100ZILOGZilog’s products are not authorized for use as critical compo-nents in life support devices or system

5-1Z16C30 USC®USER'S MANUALZILOGUM97USC01005.1 INTRODUCTIONUSER’s MANUALCHAPTER 5SERIAL MODES AND PROTOCOLSThe main advantage of USC® family memb

5-2Z16C30 USC®USER'S MANUALUM97USC0100ZILOG5.2 ASYNCHRONOUS MODES (Continued)Minimum 1 Bit Time(except for "Shaving")5 to 8 Data Bits,

Z16C30 USC®USER'S MANUALiiiZILOGUM97USC0100CHAPTER TITLE AND SUBSECTIONS PAGE5.15 HDLC/SDLC Loop Mode ...

5-3Z16C30 USC®USER'S MANUALZILOGUM97USC0100Synchronous applications vary considerably in terms ofthe line state between messages. In half-duplex

5-4Z16C30 USC®USER'S MANUALUM97USC0100ZILOGMay be Flags, Mark,Space, or Not DrivenDataFlag(7E)Flag(7E)CRCDataFlag(7E)FrameSuppose that the Data p

5-5Z16C30 USC®USER'S MANUALZILOGUM97USC0100This relatively simple technique allows transmission of anykind of data and assures uniqueness of the

5-6Z16C30 USC®USER'S MANUALUM97USC0100ZILOG5.5 THE MODE REGISTERS (CMR, TMR AND RMR) (Continued)Later sections describe each of these modes and

5-7Z16C30 USC®USER'S MANUALZILOGUM97USC01005.5.1 Enabling and Disabling the Receiverand TransmitterThe TxEnable and RxEnable fields (TMR1-0 and

5-8Z16C30 USC®USER'S MANUALUM97USC0100ZILOG5.5.2 Character Length (Continued)When RxLength is less than eight in synchronous modesincluding HDLC

5-9Z16C30 USC®USER'S MANUALZILOGUM97USC01005.6 ASYNCHRONOUS MODESoftware can select classic asynchronous operation forboth the Transmitter and t

5-10Z16C30 USC®USER'S MANUALUM97USC0100ZILOG5.6.1 Break ConditionsA Break condition is a period of Space (zero) state on anAsync line, that’s lo

5-11Z16C30 USC®USER'S MANUALZILOGUM97USC01005.8 NINE-BIT MODEThis mode is compatible with various equipment includingsome Intel single-chip micr

5-12Z16C30 USC®USER'S MANUALUM97USC0100ZILOG5.9 EXTERNAL SYNC MODESoftware can select this mode only for the Receiver, byprogramming the RxMode

Z16C30 USC®USER'S MANUALivZILOGUM97USC0100CHAPTER TITLE AND SUBSECTIONS PAGEChapter 7 Interrupts7.1 Introduction ...

5-13Z16C30 USC®USER'S MANUALZILOGUM97USC0100After the CRC, or immediately if CMR15 or TMR8 is 0, inMonosync mode the Transmitter sends the Sync c

5-14Z16C30 USC®USER'S MANUALUM97USC0100ZILOG5.11 TRANSPARENT BISYNC MODEThis mode is more specific to the Transparent Mode optionof IBM Corp.’s

5-15Z16C30 USC®USER'S MANUALZILOGUM97USC01005.12 SLAVED MONOSYNC MODEThis mode applies only to the Transmitter. Software selectsit by programmin

5-16Z16C30 USC®USER'S MANUALUM97USC0100ZILOG5.13 IEEE 802.3 (ETHERNET) MODESoftware can select this mode for the Transmitter and theReceiver, by

5-17Z16C30 USC®USER'S MANUALZILOGUM97USC0100As in other synchronous modes, the MSBit of theTxSubMode field (CMR15) controls whether the Transmit-

5-18Z16C30 USC®USER'S MANUALUM97USC0100ZILOG5.14 HDLC/SDLC MODESoftware can select this mode for both the Transmitter andthe Receiver, by writin

5-19Z16C30 USC®USER'S MANUALZILOGUM97USC0100CMR7-4 Address/Control Processingxx00 The Receiver doesn’t handle the Address or Contro

5-20Z16C30 USC®USER'S MANUALUM97USC0100ZILOG5.14.2 Frame Length ResidualsThe Receiver detects and strips inserted zeroes, Flags,and Aborts befor

5-21Z16C30 USC®USER'S MANUALZILOGUM97USC01005.15 HDLC/SDLC LOOP MODEThis mode applies only to the Transmitter. Software canselect it by programm

5-22Z16C30 USC®USER'S MANUALUM97USC0100ZILOG5.15 HDLC/SDLC LOOP MODE (Continued)OnLoop stays 1 unless the part is reset or software pro-grams th

Z16C30 USC®USER'S MANUALvZILOGUM97USC0100CHAPTER TITLE AND SUBSECTIONS PAGEAppendix A Appendix ChangesA.1 Introduction ...

5-23Z16C30 USC®USER'S MANUALZILOGUM97USC0100If the TxCRCatEnd bit (TMR8) is 1 and the TxMode field(CMR11-8) specifies a synchronous mode, the Tra

5-24Z16C30 USC®USER'S MANUALUM97USC0100ZILOG5.16 CYCLIC REDUNDANCY CHECKING (Continued)RxFIFOData InFlag/AbortDetect Logic,Incl. Shift RegisterS

5-25Z16C30 USC®USER'S MANUALZILOGUM97USC01005.17 PARITY CHECKINGA USC channel can handle a Parity bit in each character ineither asynchronous or

5-26Z16C30 USC®USER'S MANUALUM97USC0100ZILOG5.18 STATUS REPORTINGThe most important status reported by the Transmitter andReceiver is available

5-27Z16C30 USC®USER'S MANUALZILOGUM97USC0100Figure 5-10. How a USC Channel Provides the “Queued” Status Bits in the RCSRStart for RxBound,Abort/

5-28Z16C30 USC®USER'S MANUALUM97USC0100ZILOG5.18.1 Detailed Status in the TCSRPreSent: The Transmitter sets this bit (TCSR7) in a syn-chronous m

5-29Z16C30 USC®USER'S MANUALZILOGUM97USC0100Figure 5-12. The Receive Command/Status Register (RCSR)14 13 12 11 10 9 8 7 6 5 4 3 2 1 015ExitedHun

5-30Z16C30 USC®USER'S MANUALUM97USC0100ZILOG5.18 STATUS REPORTING (Continued)This bit is not associated with a particular point in thereceived d

5-31Z16C30 USC®USER'S MANUALZILOGUM97USC0100RxOver: The Receiver queues this bit through the RxFIFOwith each received character. It sets the bit

5-32Z16C30 USC®USER'S MANUALUM97USC0100ZILOG5.19 DMA SUPPORT FEATURES (Continued)A channel loads the value from the TCLR into the TransmitCharac