Zilog Z16C30 Manual de usuario descargar pdf (Pagina 7)

Z16C30 USC

USER'S MANUAL

iii

ZILOG

UM97USC0100

CHAPTER TITLE AND SUBSECTIONS PAGE

5.15 HDLC/SDLC Loop Mode ................................................................................. 5-21

5.16 Cyclic Redundancy Checking......................................................................... 5-22

5.17 Parity Checking ............................................................................................... 5-25

5.18 Status Reporting .............................................................................................. 5-26

5.18.1 Detailed Status in the TCSR ................................................................. 5-28

5.18.2 Detailed Status in the RCSR ................................................................. 5-29

5.19 DMA Support Features .................................................................................... 5-31

5.19.1 The Character Counters ....................................................................... 5-31

5.19.2 The RCC FIFO ...................................................................................... 5-35

5.19.3 Transmit Control Blocks........................................................................ 5-36

5.19.4 Receive Status Blocks .......................................................................... 5-38

5.19.5 Finding the End of a Received Frame .................................................. 5-39

5.20 Commands ...................................................................................................... 5-40

5.21 Resetting a USC Channel................................................................................ 5-44

5.22 The Data Registers and the FIFO's ................................................................. 5-45

5.22.1 Accessing the TDR & RDR ................................................................... 5-45

5.22.2 TxFIFO and RxFIFO Operation ............................................................. 5-45

5.22.3 Fill Levels .............................................................................................. 5-46

5.22.4 DMA & Interrupt Request Levels .......................................................... 5-46

5.23 Handling Overruns & Underruns ..................................................................... 5-47

5.23.1 Tx Underruns ........................................................................................ 5-47

5.23.2 Rx Overruns .......................................................................................... 5-47

5.23.3 Rx Overrun Scribbling .......................................................................... 5-48

5.23.4 Fill Level Correctness & Extra Bytes..................................................... 5-48

5.24 Between Frames, Messages, or Characters ................................................... 5-49

5.24.1 Synchronous Transmission................................................................... 5-49

5.24.2 Async Transmission.............................................................................. 5-49

5.24.3 Synchronous Reception ....................................................................... 5-51

5.25 Synchronizing Frames/Messages with Software Response............................ 5-51

Chapter 6 Direct Memory Access (DMA) Interfacing

6.1 Introduction ....................................................................................................... 6-1

6.2 Flyby vs. Flowthrough DMA Operation.............................................................. 6-1

6.3 DMA Requests by the Receiver & Transmitter .................................................. 6-6

6.3.1 Programming the DMA Request Levels ................................................. 6-7

6.4 DMA Acknowledge Signals ............................................................................... 6-8

6.5 Separating Received Frames in Memory .......................................................... 6-8

UM009402-0201

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Zilog Z16C30 Manual de usuario Pagina 7

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