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SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
153
These bits control the number of bits in each byte transferred to the transmit buffer. Bits sent must
be right justified with the least significant bits first.
The Five Or Less mode allows transmission of one to five bits per character. For five or fewer bits
per character, the data character must be formatted as shown below in Table 5-5. In the Six or
Seven Bits/Character modes, unused data bits are ignored.
Bit 4: Send Break control bit
When set, this bit forces the TxD output to send continuous 0s beginning with the following trans-
mit clock, regardless of any data being transmitted at the time. This bit functions whether or not
the transmitter is enabled. When reset, TxD continues to send the contents of the Transmit Shift
register, which might be syncs, data, or all 1s. If this bit is set while in the X21 mode (Monosync
and Loop mode selected) and character synchronization is achieved in the receiver, this bit is auto-
matically reset and the transmitter begins sending syncs or data. This bit is also reset by a channel
or hardware reset.
Bit 3: Transmit Enable
Data is not transmitted until this bit is set, and the TxD output sends continuous 1s unless Auto
Echo mode or SDLC Loop mode is selected. If this bit is reset after transmission starts, the trans-
mission of data or sync characters is completed. If the transmitter is disabled during the transmis-
sion of a CRC character, sync or flag characters are sent instead of CRC. This bit is reset by a
channel or hardware reset.
Transmit Bits per Character
Bit 7 Bit 6
0 0 5 or less bits/character
0 1 7 bits/character
1 0 6 bits/character
1 1 8 bits/character
Note: For five or less bits per character selection in
WR5, the following encoding is used in the data sent
to the transmitter. D is the data bit(s) to be sent.
D7 D6 D5 D4 D3 D2 D1 D0
1 1 1 1 0 0 0 D Sends one data bit
1 1 1 0 0 0 D D Sends two data bits
1 1 0 0 0 D D D Sends three data bits
1 0 0 0 D D D D Sends four data bits
0 0 0 D D D D D Sends five data bits
- SCC/ESCC 1
- UM010903-0515 2
- Revision History 3
- Table of Contents 4
- SCC’s Capabilities 9
- User Manual 13
- SCC Block Diagram 13
- Pin Descriptions 14
- Z85X30 DIP Pin Assignments 17
- Z85X30 PLCC Pin Assignments 18
- Z80X30 DIP Pin Assignments 19
- Interfacing the SCC/ESCC 24
- Z80X30 Write Cycle Timing 25
- Z80X30 Register Access 28
- Z80C30 Register Enhancement 31
- Z80230 Register Enhancements 32
- Z80X30 Reset 33
- Z85X30 Interface Timing 34
- Z85X30 Read Cycle Timing 35
- Z85X30 Write Cycle Timing 35
- D7-D0 Vector 36
- Z85X30 Register Access 37
- Z85C30 Register Enhancement 39
- Z85X30 Reset 41
- Interface Programming 42
- I/O Programming Introduction 43
- Interrupts 43
- External/Status Channel A 44
- Receive Channel B 44
- Transmit Channel B 44
- * Always 0 In B Channel 47
- Daisy-Chain Resolution 48
- Interrupt Acknowledge 51
- The Receiver Interrupt 52
- Receive Interrupts Disabled 53
- Conditio 56
- External/Status Interrupts 63
- Break/Abort 65
- Transmit Underrun/EOM 65
- CTS/DCD 66
- Zero Count 66
- Sync/Hunt 66
- Block/DMA Transfer 67
- SYNC Modes 68
- ASYNC Modes 68
- Wait On Receive 69
- DMA Requests 70
- DMA Request On Receive 74
- AD7-AD0 Receive DataWR8 75
- Test Functions 76
- Introduction 78
- Baud Rate Generator 78
- Data Encoding/Decoding 81
- Clock Selection 90
- Clock Multiplexer 92
- BRG Clock Source = /RTXC 93
- Crystal Oscillator 94
- Data Communication Modes 95
- Transmit Data Path 96
- Asynchronous Mode 99
- Asynchronous Transmit 100
- Asynchronous Receive 103
- Asynchronous Initialization 105
- Reg Bit No Description 107
- WR4 3 (=0) select sync mode 107
- State Changes in One 113
- /RTxC Clock Cycle 113
- SDLC Transmit 121
- SDLC Receive 127
- SDLC Frame Status FIFO 133
- Frame Status FIFO Circuitr 135
- Interface 135
- SDLC Loop Mode 137
- SDLC Loop Mode Receive 140
- SDLC Loop Mode Transmit 140
- Register Descriptions 143
- Write Registers 145
- Definition) 149
- Z85X30 Register Map 151
- Time Constant 175
- Clock Frequency 175
- Read Registers 181
- Read Register 1 185
- Read Register 2 187
- Read Register 3 188
- Read Register 8 191
- Read Register 10 192
- Read Register 12 193
- Read Register 13 194
- Read Register 15 194
- Application Notes 195
- Abstract 217
- Features 217
- Discussion 217
- Interfaces 218
- Z180 to Memory Interface 218
- EPROM Interface 220
- SRAM Interface 222
- SRAM Read Cycle 222
- SRAM Write Cycle 223
- Memory Interface Logic 223
- Physical Memory Address Map 225
- Z180 to I/O Interface 226
- Z180 I/O Write Cycle Timing 227
- Z180 to SCC Interface 230
- CPU Hardware Interfacing 230
- Data Bus Signals 230
- System Control Signals 230
- Interrupt Control 231
- SCC I/O Operation 231
- Read Cycle Timing 231
- Write Cycle Timing 232
- SCC Interrupt Operation 232
- Input/Output Cycles 234
- Z180 MPU to SCC Interface 234
- SCC I/O Read/Write Cycle 235
- I/O Read Cycle 235
- I/O Write Cycle 235
- Using EPLD 242
- System Checkout 243
- Software Considerations 244
- SCC Read Cycle Proof 244
- SCC Write Cycle Proof 244
- Interrupt Acknowledge Cycle 244
- (Continued) 246
- Summary 256
- General Description 257
- Processor 258
- Address Map 260
- (PBA)+511 269
- Serial Interfacing 270
- DMA channel 272
- Jumper Summary 276
- Control EPLD for 186 Board 278
- SCC EPLD for 186 Board 279
- DMA EPLD for 186 Board 280
- NMI Field for 186 Board 281
- Operation 295
- ESCC Controller 318
- Questions and Answers 382
- Customer Support 394
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