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SCC/ESCC
User Manual
UM010903-0515 Application Notes
251
Table lists the conventional descriptions for the power connections.
Processor
The 80186 CPU can operate at speeds up to
16 MHz. To use the CPU clock for accurate serial bit clocking, a 9.8304 MHz CPU clock can be
used. The crystal connected to the processor is 2X the operating frequency.
The processor’s 1 MB address space is well-filled, if the maximum RAM complement is
installed. Of the integrated Chip Select outputs provided by the 80186, the UCS
is used for the
EPROMs and the PCS6
-PCS0 outputs are used for the datacom
controllers. A hardware address decoder is used for the SRAMs instead of the 80186’s LCS
and
MCS3
-MCS0 outputs because the RAMs must be accessible to the on-chip DMA function of the
ISCC and IUSC as well as the 80186 CPU.
The 80186 CPU does not decodes addresses from external bus masters. Both 8-bit and 16-bit
accesses are provided for RAM. The EPROMs are only accessible to the 80186 CPU.
The 80186’s mid-range memory chip select feature (specifically, the MCS2
output) provides soft-
ware a way to hardware Reset the ISCC, IUSC, and (M)USC. This allows your program to operate
as if it were in a target system starting from Reset, including the initial write to the Bus Configura-
tion Register (BCR).
The 80186’s two integrated DMA channels can be used for any of the four or six serial data
streams in the B side of the (E)SCC and the (M)USC.
The DMA EPLD derives requests for the 80186’s two DMA channels from six inputs, two each for
(E)SCC channel B and the one or two channels in the (M)USC.
It asserts DREQ0 and DREQ1 (High) if any of the inputs for that channel is Low, and the 80186 is
not performing an Interrupt Acknowledge cycle.
Jumper blocks J22, J23, J24, and J29 control the assignment of the 80186’s internal DMA control-
lers, including provision for a clipped Tx request which is needed if a standard SCC is installed in
place of the ESCC. Table lists the 80186 DMA Jumper Connections and various possibilities.
If more than one channel among the ESCC B and (M)USC are enabled for one of the 80186’s
internal DMA channels, software must ensure that only one of the enabled devices makes requests
during a given block transfer. This can be done by leaving an entire Receiver or Transmitter idle or
disabled, or by programming the device so that the DMA request is not output on the pin.
Power Connections
Connection Circuit Device
Power V
CC
V
DD
Ground GND V
SS
- SCC/ESCC 1
- UM010903-0515 2
- Revision History 3
- Table of Contents 4
- SCC’s Capabilities 9
- User Manual 13
- SCC Block Diagram 13
- Pin Descriptions 14
- Z85X30 DIP Pin Assignments 17
- Z85X30 PLCC Pin Assignments 18
- Z80X30 DIP Pin Assignments 19
- Interfacing the SCC/ESCC 24
- Z80X30 Write Cycle Timing 25
- Z80X30 Register Access 28
- Z80C30 Register Enhancement 31
- Z80230 Register Enhancements 32
- Z80X30 Reset 33
- Z85X30 Interface Timing 34
- Z85X30 Read Cycle Timing 35
- Z85X30 Write Cycle Timing 35
- D7-D0 Vector 36
- Z85X30 Register Access 37
- Z85C30 Register Enhancement 39
- Z85X30 Reset 41
- Interface Programming 42
- I/O Programming Introduction 43
- Interrupts 43
- External/Status Channel A 44
- Receive Channel B 44
- Transmit Channel B 44
- * Always 0 In B Channel 47
- Daisy-Chain Resolution 48
- Interrupt Acknowledge 51
- The Receiver Interrupt 52
- Receive Interrupts Disabled 53
- Conditio 56
- External/Status Interrupts 63
- Break/Abort 65
- Transmit Underrun/EOM 65
- CTS/DCD 66
- Zero Count 66
- Sync/Hunt 66
- Block/DMA Transfer 67
- SYNC Modes 68
- ASYNC Modes 68
- Wait On Receive 69
- DMA Requests 70
- DMA Request On Receive 74
- AD7-AD0 Receive DataWR8 75
- Test Functions 76
- Introduction 78
- Baud Rate Generator 78
- Data Encoding/Decoding 81
- Clock Selection 90
- Clock Multiplexer 92
- BRG Clock Source = /RTXC 93
- Crystal Oscillator 94
- Data Communication Modes 95
- Transmit Data Path 96
- Asynchronous Mode 99
- Asynchronous Transmit 100
- Asynchronous Receive 103
- Asynchronous Initialization 105
- Reg Bit No Description 107
- WR4 3 (=0) select sync mode 107
- State Changes in One 113
- /RTxC Clock Cycle 113
- SDLC Transmit 121
- SDLC Receive 127
- SDLC Frame Status FIFO 133
- Frame Status FIFO Circuitr 135
- Interface 135
- SDLC Loop Mode 137
- SDLC Loop Mode Receive 140
- SDLC Loop Mode Transmit 140
- Register Descriptions 143
- Write Registers 145
- Definition) 149
- Z85X30 Register Map 151
- Time Constant 175
- Clock Frequency 175
- Read Registers 181
- Read Register 1 185
- Read Register 2 187
- Read Register 3 188
- Read Register 8 191
- Read Register 10 192
- Read Register 12 193
- Read Register 13 194
- Read Register 15 194
- Application Notes 195
- Abstract 217
- Features 217
- Discussion 217
- Interfaces 218
- Z180 to Memory Interface 218
- EPROM Interface 220
- SRAM Interface 222
- SRAM Read Cycle 222
- SRAM Write Cycle 223
- Memory Interface Logic 223
- Physical Memory Address Map 225
- Z180 to I/O Interface 226
- Z180 I/O Write Cycle Timing 227
- Z180 to SCC Interface 230
- CPU Hardware Interfacing 230
- Data Bus Signals 230
- System Control Signals 230
- Interrupt Control 231
- SCC I/O Operation 231
- Read Cycle Timing 231
- Write Cycle Timing 232
- SCC Interrupt Operation 232
- Input/Output Cycles 234
- Z180 MPU to SCC Interface 234
- SCC I/O Read/Write Cycle 235
- I/O Read Cycle 235
- I/O Write Cycle 235
- Using EPLD 242
- System Checkout 243
- Software Considerations 244
- SCC Read Cycle Proof 244
- SCC Write Cycle Proof 244
- Interrupt Acknowledge Cycle 244
- (Continued) 246
- Summary 256
- General Description 257
- Processor 258
- Address Map 260
- (PBA)+511 269
- Serial Interfacing 270
- DMA channel 272
- Jumper Summary 276
- Control EPLD for 186 Board 278
- SCC EPLD for 186 Board 279
- DMA EPLD for 186 Board 280
- NMI Field for 186 Board 281
- Operation 295
- ESCC Controller 318
- Questions and Answers 382
- Customer Support 394
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