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SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
149
Bit 5: Auto Enable
This bit programs the function for both the /DCD and /CTS pins. /CTS becomes the transmitter
enable and /DCD becomes the receiver enable when this bit is set to 1. However, the Receiver
Enable and Transmit Enable bits must be set before the /DCD and /CTS pins can be used in this
manner. When the Auto Enable bit is set to 0, the /DCD and /CTS pins are inputs to the corre-
sponding status bits in Read Register 0. The state of /DCD is ignored in the Local Loopback mode.
The state of /CTS is ignored in both Auto Echo and Local Loopback modes.
Bit 4: Enter Hunt Mode
This command forces the comparison of sync characters or flags to assembled receive characters
for the purpose of synchronization. After reset, the SCC automatically enters the Hunt mode
(except asynchronous). Whenever a flag or sync character is matched, the Sync/Hunt bit in Read
Register 0 is reset and, if External/Status Interrupt Enable is set, an interrupt sequence is initiated.
The SCC automatically enters the Hunt mode when an abort condition is received or when the
receiver is enabled.
Bit 3: Receiver CRC Enable
This bit is used to initiate CRC calculation at the beginning of the last byte transferred from the
Receiver Shift register to the Receive FIFO. This operation occurs independently of the number of
bytes in the Receive FIFO. When a particular byte is to be excluded from the CRC calculation, this
bit should be reset before the next byte is transferred to the Receive FIFO. If this feature is used,
care must be taken to ensure that eight bits per character is selected in the receiver because of an
inherent delay from the Receive Shift register to the CRC checker. This bit is internally set to 1 in
SDLC mode and the SCC calculates the CRC on all bits except zeros inserted between the opening
and closing flags. This bit is ignored in asynchronous modes.
Bit 2: Address Search Mode (SDLC)
Setting this bit in SDLC mode causes messages with addresses not matching the address pro-
grammed in WR6 to be rejected. No receiver interrupts occur in this mode unless there is an
address match. The address that the SCC attempts to match is unique (1 in 256) or multiple (16 in
256), depending on the state of Sync Character Load Inhibit bit. Address FFH is always recog-
nized as a global address. The Address Search mode bit is ignored in all modes except SDLC.
Bit 1: SYNC Character Load Inhibit
If this bit is set to 1 in any mode except SDLC, the SCC compares the byte in WR6 with the byte
about to be stored in the FIFO, and it inhibits this load if the bytes are equal. (Caution: this also
occurs in the asynchronous mode if the received character matches the contents of WR6.) The
SCC does not calculate the CRC on bytes stripped from the data stream in this manner. If the 6-bit
sync option is selected while in Monosync mode, the comparison is still across eight bits, so WR6
is programmed for proper operation.
If the 6-bit sync option is selected with this bit set to 1, all sync characters except the one immedi-
ately preceding the data are stripped from the message. If the 6-bit sync option is selected while in
the Bisync mode, this bit is ignored.
- SCC/ESCC 1
- UM010903-0515 2
- Revision History 3
- Table of Contents 4
- SCC’s Capabilities 9
- User Manual 13
- SCC Block Diagram 13
- Pin Descriptions 14
- Z85X30 DIP Pin Assignments 17
- Z85X30 PLCC Pin Assignments 18
- Z80X30 DIP Pin Assignments 19
- Interfacing the SCC/ESCC 24
- Z80X30 Write Cycle Timing 25
- Z80X30 Register Access 28
- Z80C30 Register Enhancement 31
- Z80230 Register Enhancements 32
- Z80X30 Reset 33
- Z85X30 Interface Timing 34
- Z85X30 Read Cycle Timing 35
- Z85X30 Write Cycle Timing 35
- D7-D0 Vector 36
- Z85X30 Register Access 37
- Z85C30 Register Enhancement 39
- Z85X30 Reset 41
- Interface Programming 42
- I/O Programming Introduction 43
- Interrupts 43
- External/Status Channel A 44
- Receive Channel B 44
- Transmit Channel B 44
- * Always 0 In B Channel 47
- Daisy-Chain Resolution 48
- Interrupt Acknowledge 51
- The Receiver Interrupt 52
- Receive Interrupts Disabled 53
- Conditio 56
- External/Status Interrupts 63
- Break/Abort 65
- Transmit Underrun/EOM 65
- CTS/DCD 66
- Zero Count 66
- Sync/Hunt 66
- Block/DMA Transfer 67
- SYNC Modes 68
- ASYNC Modes 68
- Wait On Receive 69
- DMA Requests 70
- DMA Request On Receive 74
- AD7-AD0 Receive DataWR8 75
- Test Functions 76
- Introduction 78
- Baud Rate Generator 78
- Data Encoding/Decoding 81
- Clock Selection 90
- Clock Multiplexer 92
- BRG Clock Source = /RTXC 93
- Crystal Oscillator 94
- Data Communication Modes 95
- Transmit Data Path 96
- Asynchronous Mode 99
- Asynchronous Transmit 100
- Asynchronous Receive 103
- Asynchronous Initialization 105
- Reg Bit No Description 107
- WR4 3 (=0) select sync mode 107
- State Changes in One 113
- /RTxC Clock Cycle 113
- SDLC Transmit 121
- SDLC Receive 127
- SDLC Frame Status FIFO 133
- Frame Status FIFO Circuitr 135
- Interface 135
- SDLC Loop Mode 137
- SDLC Loop Mode Receive 140
- SDLC Loop Mode Transmit 140
- Register Descriptions 143
- Write Registers 145
- Definition) 149
- Z85X30 Register Map 151
- Time Constant 175
- Clock Frequency 175
- Read Registers 181
- Read Register 1 185
- Read Register 2 187
- Read Register 3 188
- Read Register 8 191
- Read Register 10 192
- Read Register 12 193
- Read Register 13 194
- Read Register 15 194
- Application Notes 195
- Abstract 217
- Features 217
- Discussion 217
- Interfaces 218
- Z180 to Memory Interface 218
- EPROM Interface 220
- SRAM Interface 222
- SRAM Read Cycle 222
- SRAM Write Cycle 223
- Memory Interface Logic 223
- Physical Memory Address Map 225
- Z180 to I/O Interface 226
- Z180 I/O Write Cycle Timing 227
- Z180 to SCC Interface 230
- CPU Hardware Interfacing 230
- Data Bus Signals 230
- System Control Signals 230
- Interrupt Control 231
- SCC I/O Operation 231
- Read Cycle Timing 231
- Write Cycle Timing 232
- SCC Interrupt Operation 232
- Input/Output Cycles 234
- Z180 MPU to SCC Interface 234
- SCC I/O Read/Write Cycle 235
- I/O Read Cycle 235
- I/O Write Cycle 235
- Using EPLD 242
- System Checkout 243
- Software Considerations 244
- SCC Read Cycle Proof 244
- SCC Write Cycle Proof 244
- Interrupt Acknowledge Cycle 244
- (Continued) 246
- Summary 256
- General Description 257
- Processor 258
- Address Map 260
- (PBA)+511 269
- Serial Interfacing 270
- DMA channel 272
- Jumper Summary 276
- Control EPLD for 186 Board 278
- SCC EPLD for 186 Board 279
- DMA EPLD for 186 Board 280
- NMI Field for 186 Board 281
- Operation 295
- ESCC Controller 318
- Questions and Answers 382
- Customer Support 394
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