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Architectural Overview UM008007-0715
16
Z80 CPU
User Manual
Power-Down Release Cycle
The system clock must be supplied to the Z80 CPU to release the power-down state. When
the system clock is supplied to the CLK input, the Z80 CPU restarts operations from the
point at which the power-down state was implemented. The timing diagrams for the
release from power-down mode are featured in Figures 13 through 15. When the HALT
instruction is executed to enter the power-down state, the Z80 CPU also enters the HALT
state. An interrupt signal (either NMI
or ANT) or a RESET signal must be applied to the
CPU after the system clock is supplied to release the power-down state.
Figure 13. Power-Down Release Cycle, #1 of 3
Figure 14. Power-Down Release Cycle, #2 of 3
CLK
HALT
T1 T2 T3 T1
M1
T4
NMI
CLK
HALT
T1 T2 T3
M1
T4
RESET
- Z80 Microprocessors 1
- LIFE SUPPORT POLICY 2
- As used herein 2
- Document Disclaimer 2
- Revision History 3
- Table of Contents 4
- List of Figures 10
- User Manual 11
- List of Tables 12
- Architectural Overview 13
- CPU Register 14
- Special-Purpose Registers 14
- General Purpose Registers 15
- Arithmetic Logic Unit 16
- Pin Description 16
- Pin Functions 17
- • Memory read or write 19
- • I/O device read or write 19
- • Interrupt acknowledge 19
- Instruction Fetch 20
- Memory Read Or Write 21
- Input or Output Cycles 22
- Bus Request/Acknowledge Cycle 23
- HALT Exit 26
- Power-Down Acknowledge Cycle 27
- Power-Down Release Cycle 28
- Interrupt Response 29
- CPU Response 31
- Minimum System Hardware 33
- Adding RAM 34
- Memory Speed Control 35
- Example 1 39
- Example 2 39
- Example 3 39
- Example 4 40
- Programming Task Examples 41
- Programming Task Examples 43
- Z80 CPU Instructions 44
- Addressing Modes 46
- Addressing 46
- Register Addressing 49
- Implied Addressing 49
- Register Indirect Addressing 49
- One or Two Bytes 49
- Instruction Op Codes 50
- Load and Exchange 51
- Table 5. 8-Bit Load Group LD 52
- +8 is written as: 53
- Top of stack 56
- • BC is a byte counter 57
- Table 9. Block Search Group 59
- Table 12. 16-Bit Arithmetic 62
- Rotate and Shift 63
- Figure 39. Rotates and Shifts 64
- Bit Manipulation 67
- 3E32h is shown in Figure 40 68
- UM008007-0715 Input/Output 71
- Table 16. Restart Group 71
- Table 17. Input Group 72
- Z80 Instruction Set 75
- Carry Flag 76
- Add/Subtract Flag 76
- Parity/Overflow Flag 77
- Half Carry Flag 78
- Zero Flag 78
- Z80 Instruction Description 79
- 8-Bit Load Group 80
- LD r, r' 81
- 00 r 101 82
- LD r, (HL) 84
- LD r, (IX+d) 85
- LD r, (IY+d) 87
- LD (HL), r 89
- LD (IX+d), r 91
- LD (IY+d), r 93
- LD (HL), n 95
- LD (IX+d), n 96
- LD (IY+d), n 97
- LD A, (BC) 98
- LD A, (DE) 99
- LD A, (nn) 100
- LD (BC), A 101
- LD (DE), A 102
- LD (nn), A 103
- 11 0 01111 104
- 01 1 11100 104
- 01 1 11101 105
- 01 0 11100 106
- 01 0 11101 107
- 16-Bit Load Group 108
- LD dd, nn 109
- LD IX, nn 110
- LD IY, nn 111
- LD HL, (nn) 112
- LD dd, (nn) 113
- LD IX, (nn) 115
- LD IY, (nn) 116
- LD (nn), HL 117
- LD (nn), dd 118
- Z80 Instruction Description 119
- LD (nn), IX 120
- LD (nn), IY 121
- LD SP, HL 122
- LD SP, IX 123
- LD SP, IY 124
- 11 q 011q0 125
- 11 1 01101 127
- 11 0 01110 127
- 11 1 01111 128
- 11 q 010q0 129
- 11 0 01010 131
- EX DE, HL 134
- EX AF, AF′ 135
- 11 1 01001 136
- EX (SP), HL 137
- EX (SP), IX 138
- EX (SP), IY 139
- 10 0 00010 140
- ↔ BC – 1 142
- 10 1 00010 142
- 10 0 00011 144
- 10 1 00011 146
- Condition Bits Affected 147
- 10 1 01010 149
- 10 0 01011 151
- 10 1 01011 152
- 8-Bit Arithmetic Group 154
- ADD A, r 155
- ADD A, n 157
- ADD A, (HL) 158
- ADD A, (IX + d) 159
- ADD A, (IY + d) 160
- ADC A, s 161
- Description 162
- Operation 163
- SBC A, s 165
- 00 r 001 175
- INC (HL) 177
- INC (IX+d) 178
- INC (IY+d) 179
- Control Groups 182
- 00 0 11110 183
- 00 0 11111 185
- 01 0 00100 186
- 10 1 00001 187
- 01 0 00011 187
- 00 1 11111 188
- 00 1 11110 189
- 00 0 00000 190
- 01 1 10110 191
- 11 1 11010 192
- 11 1 11011 193
- 01 0 10100 194
- 01 1 10100 195
- 01 1 10101 196
- 16-Bit Arithmetic Group 197
- ADD HL, ss 198
- ADC HL, ss 200
- SBC HL, ss 202
- ADD IX, pp 204
- ADD IY, rr 206
- 00 s 110s0 208
- 00 0 11010 209
- 00 s 110s1 211
- 00 0 11011 212
- Rotate and Shift Group 214
- 00 0 11100 215
- 00 1 11100 217
- 00 0 11101 219
- 00 1 11101 221
- 11 0 11001 223
- RLC (HL) 225
- and the Carry 226
- RLC (IX+d) 227
- RLC (IY+d) 229
- 10 0 11101 232
- 76 4 10253 232
- 00 1 10101 233
- 00 1 01010 235
- 001010 01 236
- 101110 11 238
- 011101 10 239
- 01 0 10010 242
- 001110 11 245
- 01 0 11111 248
- 01 0 11110 250
- BIT b, r 253
- BIT b, (HL) 255
- BIT b, (IX+d) 257
- BIT b, (IY+d) 259
- SET b, r 261
- SET b, (HL) 263
- SET b, (IX+d) 265
- SET b, (IY+d) 266
- RES b, m 268
- Jump Group 270
- 11 0 11000 271
- JP cc, nn 272
- 00 1 00001 274
- PC after jump 275
- 00 1 00011 276
- JR NC, e 278
- 00 0 00011 280
- JR NZ, e 282
- 11 0 01011 284
- 00 1 00000 287
- Call and Return Group 289
- 11 0 01101 290
- CALL cc, nn 292
- 11 0 01001 294
- 01 0 01101 297
- 01 0 01100 299
- 11 t 111 301
- Input and Output Group 303
- IN A, (n) 304
- IN r (C) 305
- 10 0 10010 307
- 10 1 10010 309
- 10 0 10011 311
- 10 1 10011 313
- OUT (n), A 315
- OUT (C), r 316
- 10 0 11010 318
- 10 1 11010 320
- 10 0 11011 322
- 10 1 11011 324
- Customer Support 326
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