Zilog EZ80190 Manual de usuario descargar pdf (Pagina 16)

eZ80190 Development Kit

User Manual

eZ80Acclaim! Development Platform UM014108-0810

Table 2. eZ80Acclaim!

Development Platform

Peripheral Bus Connector Identification—JP1

Pin # Symbol Signal Direction Active Level

eZ801900100ZCO

Signal

1 A6 Bidirectional Yes

2 A0 Bidirectional Yes

3 A10 Bidirectional Yes

4 A3 Bidirectional Yes

5GND

7 A8 Bidirectional Yes

8 A7 Bidirectional Yes

9 A13 Bidirectional Yes

10 A9 Bidirectional Yes

11 A15 Bidirectional Yes

12 A14 Bidirectional Yes

13 A18 Bidirectional Yes

14 A16 Bidirectional Yes

15 A19 Bidirectional Yes

Notes:

1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from

this table. The entire interface is represented in the eZ80190 Module Schematic Diagrams

pages 66 through 73.

2. The Power and Ground nets are connected directly to the eZ801900100ZCO device.

Additional note: external capacitive loads on RD

, WR, IORQ, MREQ, D0–D7 and A0–A23 should

be below 10 pF to satisfy the timing requirements for the eZ80

CPU. All unused inputs should be

pulled to either V

or GND, depending on their inactive levels to reduce power consumption and

to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in

the eZ80F91’s Peripheral Power-Down Register.

1 2 ... 11 12 13 14 15 16 17 18 19 20 21 ... 86 87

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Zilog EZ80190 Manual de usuario Pagina 16