Zilog EZ80190 Manual de usuario descargar pdf (Pagina 19)

eZ80190 Development Kit

User Manual

UM014108-0810 Operational Description

I/O Connector (JP2)

Figure 7 illustrates the pin layout of the eZ80Acclaim!

Development Plat-

form’s I/O Connector in the 50-pin header. The I/O Connector is located at

position JP2 on the eZ80Acclaim!

Development Platform. Table 3

describes the pins and their functions.

46 RD Bidirectional Low Yes

47 WR

Bidirectional Low Yes

48 INSTRD

Input Low Yes

49 BUSACK

Input Pull-Up 10 K¾; Low Yes

50 BUSREQ

Output Pull-Up 10 K¾; Low Yes

Table 2. eZ80Acclaim!

Development Platform

Peripheral Bus Connector Identification—JP1

(Continued)

Pin # Symbol Signal Direction Active Level

eZ801900100ZCO

Signal

Notes:

1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from

this table. The entire interface is represented in the eZ80190 Module Schematic Diagrams

pages 66 through 73.

2. The Power and Ground nets are connected directly to the eZ801900100ZCO device.

Additional note: external capacitive loads on RD

, WR, IORQ, MREQ, D0–D7 and A0–A23 should

be below 10 pF to satisfy the timing requirements for the eZ80

CPU. All unused inputs should be

pulled to either V

or GND, depending on their inactive levels to reduce power consumption and

to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in

the eZ80F91’s Peripheral Power-Down Register.

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 86 87

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Zilog EZ80190 Manual de usuario Pagina 19