Zilog EZ80190 Manual de usuario descargar pdf (Pagina 18)

eZ80190 Development Kit

User Manual

eZ80Acclaim! Development Platform UM014108-0810

31 CS0 Input Low Yes

32 CS1

Input Low Yes

33 CS2

Input Low Yes

34 D0 Bidirectional Yes

35 D1 Bidirectional Yes

36 D2 Bidirectional No

37 D3 Bidirectional Yes

38 D4 Bidirectional Yes

39 D5 Bidirectional Yes

40 GND

41 D7 Bidirectional Yes

42 D6 Bidirectional Yes

43 MREQ

Bidirectional Low Yes

44 IORQ

Bidirectional Low Yes

45 GND

Table 2. eZ80Acclaim!

Development Platform

Peripheral Bus Connector Identification—JP1

(Continued)

Pin # Symbol Signal Direction Active Level

eZ801900100ZCO

Signal

Notes:

1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from

this table. The entire interface is represented in the eZ80190 Module Schematic Diagrams

pages 66 through 73.

2. The Power and Ground nets are connected directly to the eZ801900100ZCO device.

Additional note: external capacitive loads on RD

, WR, IORQ, MREQ, D0–D7 and A0–A23 should

be below 10 pF to satisfy the timing requirements for the eZ80

CPU. All unused inputs should be

pulled to either V

or GND, depending on their inactive levels to reduce power consumption and

to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in

the eZ80F91’s Peripheral Power-Down Register.

1 2 ... 13 14 15 16 17 18 19 20 21 22 23 ... 86 87

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Zilog EZ80190 Manual de usuario Pagina 18