Zilog EZ80F91 Manual de usuario descargar pdf (Pagina 20)

eZ80F91 Development Kit

User Manual

UM014220-0508 eZ80 Development Kit

I/O Connector

Figure 7 displays the pin layout of the I/O Connector in the 50-pin header,

located at position JP2 on the eZ80Acclaim!

Development Kit. Table 4

on page 17 identifies the pins and their functions.

45 GND

46 RD

Bidirectional Low Yes

47 WR

Bidirectional Low Yes

48 INSTRD

Input Low Yes

49 BUSACK

Input Pull-Up 10 kΩ; Low Yes

50 BUSREQ

Output Pull-Up 10 kΩ; Low Yes

Notes

1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from

this table. The entire interface is represented in the eZ80F91 Module Schematics, see Figure 23

through Figure 25.

2. The Power and Ground nets are connected directly to the eZ80F91 device.

3. Additional note: external capacitive loads on RD

, WR, IORQ, MREQ, D0–D7 and A0–A23

should be below 10 pF to satisfy the timing requirements for the eZ80

CPU. All unused inputs

should be pulled to either V

or GND, depending on their inactive levels to reduce power con-

sumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deacti-

vated via software in the eZ80F91’s Peripheral Power-Down Register.

Table 3. eZ80Acclaim!

Development Kit Peripheral Bus Connector Identification—

JP1

1,3

(Continued)

Pin # Symbol Signal Direction Active Level eZ80F91 Signal

1 2 ... 15 16 17 18 19 20 21 22 23 24 25 ... 77 78

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