Zilog Z80380 Manual de usuario descargar pdf (Pagina 43)

5-9

Z380

™

USER'S MANUAL

ZILOG

DC-8297-03

has to be an even number (D0 = 0) in Word mode transfer,

and a multiple of four in Long Word mode (D1 and D0 are

both 0). Also, in Word or Long Word Block transfer,

memory pointer values are recommended to be even

numbers so the number of the transactions will be mini-

mized.

Note that regardless of the Z380’s operation mode, Native

or Extended, memory pointer increment/decrement will be

done in modulo 2

. For example, if the operation is LDI and

HL31-HL0 (HLz and HL) hold 0000FFFF, after the opera-

tion the value in the HL31-HL0 will be 0010000.

Table 5-8. Block Transfer and Search Group

Instruction Name Format

Compare and Decrement CPD

Compare, Decrement and Repeat CPDR

Compare and Increment CPI

Compare, Increment and Repeat CPIR

Load and Decrement LDD

Load , Decrement and Repeat LDDI

Load and Increment LDI

Load, Increment and Repeat LDIR

Load and Decrement in Word/Long Word LDDW

Load, Decrement and Repeat in Word/Long Word

LDDRW

Load and Increment in Word/Long Word LDIW

Load, Increment and Repeat in Word/Long Word

LDIRW

5.5.4 8-bit Arithmetic and Logical Group

This group of instructions (Table 5-9) perform 8-bit arith-

metic and logical operations. The Add, Add with Carry,

Subtract, Subtract with Carry, AND, OR, Exclusive OR, and

Compare takes one input operand from the accumulator

and the other from a register, from immediate data in the

instruction itself, or from memory. For memory addressing

modes, follows are supported—Indirect Register, Indexed,

and Direct Address—except multiplies, which returns the

16-bit result to the same register by multiplying the upper

and lower bytes of one of the register pair (BC, DE, HL, or

SP).

The Increment and Decrement instructions operate on

data in a register or in memory; all memory addressing

modes are supported. These instructions operate only on

the accumulator—Decimal Adjust, Complement, and Ne-

gate. The final instruction in this group, Extend Sign, sets

the CPU flags according to the computed result.

The EXTS instruction extends the sign bit and leaves the

result in the HL register. If it is in Long Word mode, HLz

(HL31-HL16) portion is also affected.

The TST instruction is a nondestructive AND instruction. It

ANDs "A" register and source, and changes flags accord-

ing to the result of operation. Both source and destination

values will be preserved.

Table 5-9. Supported Source/Destination for 8-Bit Arithmetic and Logic Group

src/

Instruction Name Format dst A B C D E H L IXH IXL IYH IYL n (HL) (IX+d) (IY+x)

Add With Carry (Byte) ADC A,src src √ √ √√ √√√√ √ √ √ √√ √ √

Add (Byte) ADD A,src src √ √ √√ √√√√ √ √ √ √√ √ √

AND AND [A,]src src √ √ √√ √√√√ √ √ √ √√ √ √

Compare (Byte) CP [A,]src src √ √ √√ √√√√ √ √ √ √√ √ √

Complement Accumulator CPL [A] dst √

Decimal Adjust Accumulator DAA dst √

Decrement (Byte) DEC dst dst √ √ √√ √√√√ √ √ √ √√ √ √

Extend Sign (Byte) EXTS [A] dst √

Increment (Byte) INC dst dst √ √ √√ √√√√ √ √ √ √√ √ √

Multiply (Byte) MLT src Note 1

Negate Accumulator NEG [A] dst √

OR OR [A,]src src √ √ √√ √√√√ √ √ √ √√ √ √

Subtract with Carry (Byte) SBC A,src src √ √ √√ √√√√ √ √ √ √√ √ √

Subtract (Byte) SUB [A,]src src √ √ √√ √√√√ √ √ √ √√ √ √

Nondestructive Test TST dst src √ √ √√ √√√ √√

Exclusive OR XOR [A,]src src √ √ √√ √√√√ √ √ √ √√ √ √

Note 1: dst = BC, DE, HL, or SP.

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