Zilog Z16C35 Manual de usuario descargar pdf (Pagina 104)

ISCC

User Manual

UM011002-0808

5.4.4 Write Register 3 (Receive Parameters and Control)

This register contains the control bits and parameters for the receiver logic as illustrated in

Figure 5-5.

Figure 5–34. Write Register 3

Bit 7 and 6 select the Receiver Bits/Character

The state of these two bits determines the number of bits to be assembled as a character in

the received serial data stream. The number of bits per character can be changed while a

character is being assembled but only before the number of bits currently programmed is

reached. Unused bits in the Received Data Register (RR8) are set to “1” in asynchronous

modes. In synchronous modes and SDLC modes, the ISCC merely transfers an 8-bit sec-

tion of the serial data stream to the receive FIFO at the appropriate time. Table 5-5 lists the

number of bits per character in the assembled character format.

Table 5–27. Receive Bits per Character

D7 D6 Bits/Character

0 0 5

0 1 7

1 0 6

1 1 8

Write Register 3

D6D7 D5 D4 D3 D2 D1 D0

Rx Enable

Sync Character Load Inhibit

Address Search Mode (SDLC)

Rx CRC Enable

Enter Hunt Mode

Auto Enables

Rx 5 Bits/Character

Rx 7 Bits/Character

Rx 6 Bits/Character

Rx 8 Bits/Character

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Zilog Z16C35 Manual de usuario Pagina 104