Zilog Z16C35 Manual de usuario descargar pdf (Pagina 181)

Application Note

The Z180™ Interfaced with the SCC at MHZ

7-4

EPROM INTERFACE

During an Opcode fetch cycle, data sampling of the bus is

on the rising PHI clock edge of T3 and on the falling edge

of T3 during a memory read cycle. Opcode fetch cycle data

sample timing is half a clock cycle earlier. Table 2 shows

how a memory read cycles’ timing requirements are easier

than an opcode fetch cycle by half a PHI cycle time. If the

timing requirements for an Opcode fetch cycle meet

specifications, the design satisfies the timing requirements

for a memory read cycle.

Table 2 has some equations for an opcode fetch, memory

read/write cycle.

The propagation delay for the decoded address and gates

in the previous calculation is zero. Hence, on the real

design, subtracting another 20-30 ns to pay for

propagation delays, is possible. The 27C256 provides the

EPROM for this board. Typical timing parameters for the

27C256 are in Table 3.

SRAM Interface

Table 4 has timing parameters for 256K bit SRAM for this

design.)

SRAM Read Cycle.

An SRAM read cycle shares the

same considerations as an EPROM interface.

Like EPROM, SRAMs’ “access time” applies /G to data

valid, and “/E active to data valid” is shorter than “access

time.” This design allows the use of a 150 ns access time

SRAM by adding one wait state (using the on-chip wait

state generator of the Z180). The circuit is common to the

EPROM memory read cycle.

No wait states are necessary if there is a 85 ns, or faster,

access time by using SRAMs. Since the Z180 has on-chip

MMU with 85 ns or faster SRAM just copy the contents of

EPROM (application program starts at logical address

0000h) into SRAM after power on. Set up the MMU to

SRAM area to override the EPROM area and stop

Table 2. Parameter Equations (10 MHz) Opcode Fetch/Memory Read/Write Cycle

Parameters Z180 Equation Value Units

Address Valid to Data Valid (Opcode Fetch) 2(1+w)tcyc-tAD-tDRS 105+100w min ns

Address Valid to Data Valid (Memory Read 2(1+w)tcyc+tCHW+tcf-tAD-tDRS 155+100w min ns

/MREQ Active to Data Valid (Opcode Fetch) (1+w)tcyc+tCLW-tMED1-tDRS 55+100w min ns

/MREQ Active to Data Valid (Memory Read) (2+w)tcyc-tMED1-tDRS 105+100w min ns

/RD Active to Data Valid (Opcode Fetch) (1+w)tcyc+tCLW-tRRD1-tDRS 55+100w min ns

/RD Active to Data Valid (Memory Read) (2+w)tcyc-tRRD1-tDRS 105+100w min ns

Memory Write Cycle /WR Pulse Width tWRP+w*tcyc 110+100w min ns

Note:

* w is the number of wait states.

Table 3. EPROM (27C256) Key Timing Parameters

(Values May Vary Depending On Mfg.)

Access Time

170 ns 200 ns 250 ns

Parameter Max Max Max

Addr Access Time 170 200 250

/E to Data Valid 170 200 250

/OE to Data Valid 75 75 100

Note:

Table 3 shows “Access Time” as applying /E to data valid.

“/OE active to data valid” is shorter than “address access time”.

Hence, the interface logic for the EPROM is: Realize a 170 ns or

faster EPROM access time by adding one wait state (using the

on-chip wait state generator of the Z180). A 200 ns requirement

uses two wait states for memory access.

Table 4. 256K SRAM Key Timing parameters

(Values May Vary Depending On Mfg.)

Access Time

85 ns 100 ns 150 ns

Parameter Min Min Min

Read Cycle:

/E to Data Valid 85 100 150

/G to Data Valid 45 40 60

Write Cycle:

Write Cycle Time 85 100 150

Addr Valid to End of Write 75 80 100

Chip Select to End of Write 75 80 100

Data Select to End of Write 40 40 60

Write Pulse Width 60 60 90

Addr Setup Time 0 0 0

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Zilog Z16C35 Manual de usuario Pagina 181

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Zilog Z16C35 Manual de usuario Pagina 181

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