Zilog Z16C35 Manual de usuario descargar pdf (Pagina 139)

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bit is set). This status information is contained in bits 1, 2, and 3 of the interrupt vector.

The other interrupt vector bits remain unmodified.

Bit 3, when set, enables the interrupt from the Receiver A DMA.

Bit 2, when set, enables the interrupt from the Transmitter A DMA.

Bit 1, when set, enables the interrupt from the Receiver B DMA.

Bit 0, when set, enables the interrupt from the Transmitter B DMA.

5.6.4 Interrupt Vector Register

This register holds the interrupt vector for the DMA cell. The value programmed into this

the DMA interrupt sources is the highest priority pending interrupt. Note that bits 1, 2, and

Table 5–36. Interrupt Vector Status Encoding

IV3 IV2 IV1 Interrupt

0 0 0 No Interrupt Pending

0 0 1 Not Possible

0 1 0 Not Possible

0 1 1 Not Possible

1 0 0 Rx A IP

1 0 1 Rx B IP

1 1 0 Tx A IP

1 1 1 Tx B IP

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