Zilog Z8F0130 Manual de usuario descargar pdf (Pagina 13)

eZ8

™

CPU Core

User Manual

UM012820-0810 Manual Objectives

xiii

Braces

The curly braces, { }, indicate a single register or bus created by concate-

nating some combination of smaller registers, buses, or individual bits.

•

Example: the 12-bit register address {0h, RP[7:4], R1[3:0]} is com-

posed of a 4-bit hexadecimal value (

0h) and two 4-bit register values

taken from the Register Pointer (RP) and Working Register R1.

0h is

the most significant nibble (4-bit value) of the 12-bit register, and

R1[3:0] is the least significant nibble of the 12-bit register.

Parentheses

The parentheses, ( ), indicate an indirect register address lookup.

•

Example: (R1) is the memory location referenced by the address con-

tained in the Working Register R1.

Parentheses/Bracket Combinations

The parentheses, ( ), indicate an indirect register address lookup and the

square brackets, [ ], indicate a register or bus.

•

Example: Assume PC[15:0] contains the value 1234h. (PC[15:0])

then refers to the contents of the memory location at address

1234h.

Use of the Words Set, Reset, and Clear

The word set implies that a register bit or a condition contains a logical 1.

The word reset or clear implies that a register bit or a condition contains a

logical 0. When either of these terms is followed by a number, the word

logical may not be included; however, it is implied.

Notation for Bits and Similar Registers

A field of bits within a register is designated as: Register[n:n].

•

Example: ADDR[15:0] refers to bits 15 through bit 0 of the Address.

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 ... 313 314

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Zilog Z8F0130 Manual de usuario Pagina 13