Zilog Z8F0130 Manual de usuario descargar pdf (Pagina 277)

eZ8

™

CPU Core

User Manual

UM012820-0810 Op Codes Listed Numerically

262

Op Codes Listed Numerically

Table 26 lists the eZ8 CPU instructions, sorted numerically by the Op

Code. The table identifies the addressing modes employed by the instruc-

tion, the effect upon the Flags register, the number of CPU clock cycles

required for the instruction fetch, and the number of CPU clock cycles

required for the instruction execution.

Table 26. eZ8 CPU Instructions Sorted by Op Code

Code(s)

(Hex)

Assembly

Mnemonic

Address

Mode Flags

Fetch

Cycles

Instr.

Cyclesdst src C Z S V D H

00 BRK –––––– 1 2

01 SRP src IM – – – – – – 2 2

02 ADD dst, src r r * * * * 0 * 2 3

03 ADD dst, src r Ir * * * * 0 * 2 4

04 ADD dst, src R R * * * * 0 * 3 3

05 ADD dst, src R IR * * * * 0 * 3 4

06 ADD dst, src R IM * * * * 0 * 3 3

07 ADD dst, src IR IM * * * * 0 * 3 4

08 ADDX dst, src ER ER * * * * 0 * 4 3

09 ADDX dst, src ER IM * * * * 0 * 4 3

0A DJNZ dst, RA r – – – – – – 2

Z/NZ

3/4

0b JR F, dst DA – – – – – – 2 2

0C LD dst, src r IM – – – – – – 2 2

1 2 ... 272 273 274 275 276 277 278 279 280 281 282 ... 313 314

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