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eZ8
™
CPU Core
User Manual
UM012820-0810 Architectural Overview
9
Arithmetic Logic Unit
The Arithmetic Logic Unit (ALU) performs arithmetic and logical opera-
tions on the data. The arithmetic operations include addition, subtraction,
and multiplication. The logical functions include binary logic operations,
bit shifting, and bit rotation.
0110 6 Z Zero Z = 1
0110 6 EQ Equal Z = 1
0111 7 C Carry C = 1
0111 7 ULT Unsigned Less Than C = 1
1000 8 T (or blank) Always True –
1001 9 GE Greater Than or Equal (S XOR V) = 0
1010 A GT Greater Than (Z OR (S XOR V)) = 0
1011 B UGT Unsigned Greater Than (C = 0 AND Z = 0)
1100 C NOV No Overflow V = 0
1101 D PL Plus S = 0
1110 E NZ Non-Zero Z = 0
1110 E NE Not Equal Z = 0
1111 F NC No Carry C = 0
1111 F UGE Unsigned Greater Than or
Equal
C = 0
Table 2. Condition Codes (Continued)
Binary Hex
Assembly
Mnemonic Definition Flag Test Operation
- CPU Core 1
- UM012820-0810 2
- Revision History 3
- Table of Contents 4
- Manual Objectives 10
- Manual Conventions 12
- Parentheses 13
- Safeguards 14
- Abbreviations/Acronyms 15
- Architectural Overview 16
- Fetch Unit 17
- Execution Unit 18
- Stack Pointer Registers 19
- Register Pointer 20
- Flags Register 20
- Condition Codes 23
- Arithmetic Logic Unit 24
- Byte Ordering 25
- Compatibility 26
- New Function Instructions 27
- CPU Instruction Set De 28
- Alternate Function Op Code 29
- Moved Instructions 29
- Removed Instructions 29
- Compatibility with Z8 CPU 30
- Stack Pointer Compatibility 31
- Reset Compatibility 31
- Interrupt Compatibility 31
- Address Space 32
- CPU Control Registers 33
- General-Purpose Registers 33
- Register File Organization 33
- UM012820-0810 Address Space 34
- {RP[3:0], RP[7:4] 35
- Address[3:0]} 35
- Program Memory 38
- Data Memory 39
- Interrupts 42
- Interrupt Priority 43
- Vectored Interrupt Processing 43
- Polled Interrupt Processing 46
- Software Interrupt Generation 47
- UM012820-0810 Interrupts 48
- Addressing Modes 49
- Register Addressing 50
- RP[3:0]. The full 12-bit 51
- {RP[3:0], Address[7:0]} 51
- Escaped Mode Addressing 52
- Indirect Register Addressing 54
- Indexed Addressing 56
- Direct Addressing 57
- Relative Addressing 58
- Immediate Data Addressing 59
- Illegal Instruction Traps 60
- CPU Instruction Set 62
- Assembly Language Syntax 63
- UM012820-0810 eZ8 67
- CPU Instruction Set Summary 67
- Description 86
- INSTRUCTION MNEMONIC 87
- Mnemonic 105
- Destination 105
- Op Code 105
- User Manual 107
- CALL @A4h 129
- Object Code: D4 A4 129
- UM012820-0810 CCF Instruction 131
- Sample Usage 131
- Object Code: EF 131
- UM012820-0810 DA Instruction 149
- 0011 1100 = 3Ch 149
- 0000 0110 = 06h 149
- 0100 0010 = 42h 149
- Mnemonic Destination 212
- POP R1 50 R1 — — 212
- POP @R1 51 R1 — — 212
- UM012820-0810 RCF Instruction 221
- Object Code: CF 221
- RL R1 90 R1 — — 225
- RL @R1 91 R1 — — 225
- UM012820-0810 SCF Instruction 238
- Object Code: DF 238
- Op Code Maps 273
- Figure 20. First Op Code Map 275
- Op Codes Listed Numerically 277
- Assembly and Object Code 291
- UM012820-0810 Index 305
- Customer Support 314
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