Zilog Z08470 Manual de usuario descargar pdf (Pagina 143)

UM008101-0601 Direct Memory Access

End-of-Block

After a stop or stop and interrupt on end-of-block (WR4 or WR5), where it

is necessary to perform additional operations with the DMA, write the same

sequence of commands listed immediately under “Byte Matching

(Searches)” on page 124. Table 12 on page 76 describes the contents of

various counters when stopping on end-of-block.

Auto Restart

To obtain a repetitive transfer or search using the same block length and

starting addresses originally entered, initialize the DMA including WR%

bit 5 = 1. Loading of addresses and clearing of the byte counter is auto-

matic.

When in Byte mode (or Burst mode where the Ready line is occasionally

released), it is possible to alter the starting addresses during a transfer (for

example, between bus requests) without disturbing that transfer. At the end

of this transfer, the DMA automatically loads the new addresses to the

counter and continues without interruption.

Force Ready Condition

The FORCE READY command is provided for operations such as memory-to-

memory transfer or memory search-only where no Ready line from an I/O

device is used. However, several DMA commands unforce the Ready

condition after the

FORCE READY command is written. The sequence of

command entry is therefore important. This sequence is described in the

FORCE READY command in “Write Register 6 Group” on page 105.

Pulse Generation

To obtain pulses at 256-byte intervals, after a variable offset period,

consider only the WR4 group. The INT line is used for these pulses.

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Zilog Z08470 Manual de usuario Pagina 143