Zilog Z08470 Manual de usuario descargar pdf (Pagina 38)

UM008101-0601 Counter/Timer Channels

Bit 7 = 1. Each channel is enabled to generate an interrupt request sequence

when the down-counter reaches a zero-count condition. To set the interrupt

bit to 1 in any of the four Channel Control registers an interrupt vector is

written to the CTC before operation begins. Channel interrupts may be

programmed in either Counter or Timer mode. If an updated channel

control word is written to a channel in operation, with bit 7 set, the interrupt

enable selection is not retroactive to a preceding zero-count condition.

Bit 7 = 0. Channel interrupts disabled.

Bit 6 = 1. Counter mode selected. The down-counter is decremented by

each triggering edge of the External clock (CLK/TRG) input. The prescaler

is not used.

Bit 6 = 0. Timer mode selected. The prescaler is clocked by the System

clock Φ, and the output of the prescaler in turn clocks the down-counter.

The output of the down-counter (the channel’s ZC/TO output) is a uniform

pulse train of period given by the product as shown below

4 CLK/TRG Edge

Section

R/W 1

Rising Edge

Falling Edge

3 Time Trigger* R/W 1

CLK/TRG Pulse Starts Timer

Automatic trigger when time constant is loaded

2 Time Constant R/W 1

Time Constant Follows

No Time Constant Follows

1Reset R/W1

Software Reset

Continue Operation

0 Control or Vector R/W 1

Control

Ve ct o r

Bit

Number Field R/W Value Description

*TIMER mode only

1 2 ... 33 34 35 36 37 38 39 40 41 42 43 ... 329 330

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Zilog Z08470 Manual de usuario Pagina 38