Zilog Z08470 Manual de usuario descargar pdf (Pagina 196)

UM008101-0601 Parallel Input/Output

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Four modes of port operation with interrupt-controlled handshake:

– Byte Output

– Byte Input

– Byte Bidirectional Bus (available on Port A only)

– Bit Control Mode

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Daisy-chain priority interrupt logic, allowing automatic interrupt

vectoring without external logic

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Eight outputs capable of driving darlington transistors

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Fully TTL-compatible inputs and outputs

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Single 5V supply and single-phase clock required

PIO ARCHITECTURE

Overview

Figure 1 illustrates ablock diagram of the Z80 PIO. The internal structure of

the Z80 PIO consists of a Z80 CPU bus interface, internal control logic,

Port A I/O logic, Port B I/O logic, and interrupt control logic. The CPU bus

interface logic allows the PIO to interface directly to the Z80 CPU with no

other external logic. However, address decoders and/or line buffers may be

required for large systems. The internal control logic synchronizes the CPU

data bus to the peripheral device interfaces (Port A and Port B). The two

I/O ports (A and B) are virtually identical and are used to interface directly

to peripheral devices.

Figure 2 depicts the Port I/O logic is composed of 6 registers with hand-

shake control logic. The registers include: an 8-bit data input register, an

8-bit data output register, a 2-bit mode control register, an 8-bit mask

1 2 ... 191 192 193 194 195 196 197 198 199 200 201 ... 329 330

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Zilog Z08470 Manual de usuario Pagina 196