Zilog Z08470 Manual de usuario descargar pdf (Pagina 169)

UM008101-0601 Direct Memory Access

System throughput is decreased for applications requiring frequent DMA

reprogramming or extensive interrupt service of data-independent DMA

functions. It is more efficient to transfer large blocks of repetitive data.

TIMING

The CPU As Bus Master

When the CPU is the bus master, control bytes can program the Direct

Memory Access (DMA).

Writing Control Bytes

Table 13 illustrates the disabled, enabled/inactive, or enabled/stopped

states. The enabled/inactive and enabled/stopped states are equivalent. The

DMA is programmed by being addressed as an I/O peripheral in a CPU

output instruction. The DMA can be addressed in the full 64K I/O space. To

accomplish this, three lines must be simultaneously active-Low on the ris-

ing edge of the clock:

Chip Enable

IORQ

Input/Output Request

WR Write

Figure 59 illustrates the timing required for this process. In a Z80 CPU

environment, this timing occurs automatically when the CPU and DMA are

on the same board and have no buffers, drivers, or other external gates in

series with the common CPU and DMA pins. This timing applies to the

sequential transfer, sequential transfer/search, and search-only classes of

operation. It may or may not apply to the simultaneous transfer or simulta-

neous transfer/search operations, depending on the speed of the external

devices used (see the Applications chapter).

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Zilog Z08470 Manual de usuario Pagina 169