Zilog Z08470 Manual de usuario descargar pdf (Pagina 171)

UM008101-0601 Direct Memory Access

Figure 60. CPU-to-DMA Read Cycle Requirements

The DMA As Bus Master

Sequential Transfers

In sequential transfer and transfer/search operations, which both have the

same timing, data is latched onto the bus by the rising edge of the RD sig-

nal, with standard timing this is the falling edge of T3. Data is held on the

data bus across the boundary between read and write cycles, through the

end of the following write cycle. The DMA data bus drivers become active

when RD

becomes inactive.

Figure 61 illustrates the timing for memory-to-I/O port transfers, and

Figure 62 illustrates I/O-to-memory transfers. Memory-to-memory and I/O

to-I/O transfer timings are simply permutations of these diagrams.

The default timing uses three clock cycles for memory transactions and

four clock cycles for I/O transactions, which include one automatically

inserted wait cycle between T2 and T3. If the CE

/WAIT line is pro-

grammedtoserveasaWAIT

line during the DMA’s active state, it is sam-

pled on the falling edge of T2 for memory transactions and the falling edge

of TW for I/O transactions. If CE

/WAIT is Low during this time, another T-

cycle is added, during which time the CE

/WAIT line is again sampled. The

duration of transactions can thus be indefinitely extended.

CLK

IORQ

D7–D0

1 2 ... 166 167 168 169 170 171 172 173 174 175 176 ... 329 330

Sin comentarios

Zilog Z08470 Manual de usuario Pagina 171