Zilog Z08470 Manual de usuario descargar pdf (Pagina 33)

UM008101-0601 Counter/Timer Channels

an interrupt from any CTC channel. Therefore, this signal blocks lower-

priority devices from interrupting while a higher-priority interrupting

device is being serviced by the CPU.

INT

Interrupt Request (output, open-drain, active Low). This signal goes

true when a CTC channel, which has been programmed to enable

interrupts, has a zero-count condition in its down-counter.

RESET

Reset (input, active Low). This signal stops all channels from counting

and resets interrupt enable bits in all control registers, thereby disabling

CTC-generated interrupts. The ZC/TO and INT

outputs go inactive, IEO

reflects IEI, and the CTC’s data bus output drivers go to the high-

impedance state.

CLK/TRG3–CLK/TRG0

External Clock/Timer Trigger (input, user-selectable active High or

Low). Four CLK/TRG pins correspond to the four independent CTC

channels. In the Counter mode, every active edge on this pin decrements

the down-counter. In the TIMER mode, an active edge on this pin initiates

the timing function. The user may select the active edge to be either rising

or falling.

ZC/TO2-AC/TO0

Zero Count/Timeout (output, active High). Three ZC/TO pins

correspond to CTC Channels 2 through 0. (Because of package pin

limitations Channel 3 has no ZC/TO pin.) In either COUNTER mode or

TIMER mode, when the down-counter decrements to zero, an active High

pulse appears at this pin.

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Zilog Z08470 Manual de usuario Pagina 33