Zilog Z80180 Manual de usuario descargar pdf (Pagina 124)

Z8018x

Family MPU User Manual

UM005003-0703

109

memory mapped I/O. transfers, the CKA0/DREQ0 pin automatically

functions as input pin or output pin even if it has been programmed as

output pin for CKA0. And the CKA1/TEND

0 pin functions as an input or

an output pin for TEND

0 by setting CKA1D to 1 in CNTLA1.

To initiate memory to/from I/O (and memory to/from memory mapped

I/O) DMA transfer for channel 0, perform the following operations:

1. Load the memory and I/O or memory mapped I/O source and

destination addresses into SAR0 and DAR0.

I/O addresses (not memory mapped I/O are limited to 16 bits (A0–

A15). Make sure that bits A16, A17 and A19 are

0 (A18 is a don't

care) to correctly enable the external DREQ

0 input.

2. Specify memory to/from I/O or memory to/from memory mapped I/O

mode and address increment/decrement in the SM0, SM1, DM0 and

DM1 bits of DMODE.

3. Load the number of bytes to transfer in BCR0.

4. Specify whether DREQ

0 is edge- or level-sense by programming the

DMS0 bit of DCNTL.

5. Enable or disable DMA termination interrupt with the DIE0 bit in

DSTAT.

6. Program DE0: = 1 (with DWEO

= 0 in the same access) in DSTAT

and the DMA operation begins under the control of the DREQ

0 input.

Memory to ASCI - Channel 0

Channel 0 has extra capability to support DMA transfer to/from the on-

chip two channel ASCI. In this case, the external DREQ

0 input is not

used for DMA timing. Rather, the ASCI status bits are used to generate an

internal DREQ

0 The TDRE (Transmit Data Register Empty) bit and the

RDRF (Receive Data Register Full) bit are used to generate an internal

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Zilog Z80180 Manual de usuario Pagina 124