Zilog Z80180 Manual de usuario Pagina 314
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- Tabla de contenidos
- MARCADORES
Valorado. / 5. Basado en revisión del cliente
Z8018x
Family MPU User Manual
298
UM005003-0703
Timer Data Register
Channel 1L:
Timer Data Register
Channel 1H:
Timer Reload Register
Channel 1L
Timer Reload Register
Channel 1H:
Free Running Counter:
DMA Source Address
Register Channel 0L:
DMA Source Address
Register Channel 0H:
DMA Source Address
Register Channel 0B:
DMA Destination Address
Register Channel 0L:
DMA Destination Address
Register Channel 0H:
DMA Destination Address
Register Channel 0B:
DMA Byte Count Register
Channel 0L:
DMA Byte Count Register
Channel 0H:
DMA Memory Address
Register
Channel 1L:
DMA Memory Address
Register
Channel 1H:
TMDR1L
TMDR1H
RLDR1L
RLDR1H
FRC
SAR0L
SAR0H
SAR0B
DAR0L
DAR0H
DAR0B
BCROL
BCROH
MAR1L
MAR1H
14
15
16
17
18
20
21
22
23
24
25
26
27
28
29
Table 57. Internal I/O Registers (Continued)
Register Mnemonics Address Remarks
Bits 0-2 (3) are used for SAR0B
A
19
*, A
18
, A
17
,A
16
X
X
X
X
X
X
X
X
0
0
1
1
0
1
0
1
DMA Transfer Request
DREQ
0
(external)
RDR0 (ASCI0)
RDR1 (ASCI1)
Not used
Bits 0-2 (3) are used for DAR0B
A
19
*, A
18
, A
17
,A
16
X
X
X
X
X
X
X
X
0
0
1
1
0
1
0
1
DMA Transfer Request
DREQ
0
(external)
TDR0 (ASCI0)
TDR1 (ASCI1)
Not used
* In the R1 and Z mask, these DMAC registers are expanded from 4 bits to 3 bits in the
package version of CP-68.
Read only
- Family MPU 1
- MANUAL OBJECTIVES 3
- Intended Audience 3
- Manual Organization 3
- Sections 4
- Appendices 4
- Table of Contents 5
- List of Figures 8
- UM005003-0703 10
- List of Tables 12
- Status Signals 287 14
- FEATURES 16
- GENERAL DESCRIPTION 16
- PIN DESCRIPTION 22
- ARCHITECTURE 27
- OPERATION MODES 30
- 0 and IOC is 0 32
- CPU Timing 33
- Wait State Generator 42
- Bit 7 6 5 4 44
- MWI1 MWI0 MWI1 MWI0 44
- R/W R/W R/W R/W 44
- 1, selecting the 45
- Processors Only) 46
- SLP 2nd Op Code address 50
- Add-On Features 51
- STANDBY Mode 52
- IDLE Mode 55
- STANDBY-QUICK RECOVERY Mode 56
- Internal I/O Registers 56
- –0 Reserved ? ? Reserved 67
- Memory Management Unit (MMU) 69
- Figure 25. MMU Block Diagram 71
- 0 during I/O cycles 72
- MMU Register Description 75
- 0 during RESET 77
- 1 while all bits 78
- 0. The logical 64KB 78
- 0000H to FFFFH) 78
- Interrupts 80
- Interrupt Vector Low Register 81
- 00H during RESET 82
- N/A R/W R/W R/W 83
- 1 by the El (Enable 84
- 00000H was caused by 85
- INT0 Mode 0 90
- INT0 Mode 1 91
- INT0 Mode 2 93
- 00H and 94
- INT1, INT2 95
- 0. Each is also 96
- Family MPU User Manual 100
- Dynamic RAM Refresh Control 101
- TR1 TRW* TR2 102
- DMA Controller (DMAC) 105
- 107
- DMAC Register Description 108
- DMA Register Description 118
- Bits 5–3 119
- Bits 2–0 119
- DMA Operation 119
- Memory to Memory—Channel 0 120
- 00H) transfer 122
- Memory to ASCI - Channel 0 124
- Note: X = Don’t care 125
- T1 T2 T3 T3T2T1 130
- Processors 131
- ASCI Register Description 132
- 08H, 09H) 134
- 1) these pins 149
- 1, then the CKA1/ 149
- 0. Even after the 154
- Figure 56. ASCI Clock 156
- Baud Rate Generator 158
- CSI/O Block Diagram 161
- CSI/O Registers Description 162
- Address = 0BH) 164
- Interrupt Request 166
- = 0) when 167
- PRT Block Diagram 171
- PRT Register Description 172
- 0FH, CHI, 16H, 17H) 174
- Timer Control Register (TCR) 176
- PRT Interrupts 179
- PRT and RESET 179
- Secondary Bus Interface 180
- On-Chip Clock Generator 183
- Miscellaneous 187
- Software Architecture 188
- CPU REGISTERS 190
- Accumulator (A, A') 191
- Flag Registers (F, F') 192
- Interrupt Vector Register (I) 192
- R Counter (R) 192
- Index Registers (IX, and IY) 192
- Stack Pointer (SP) 193
- Program Counter (PC) 193
- Flag Register (F) 193
- Addressing Modes 195
- Implied Register (IMP) 195
- Register Direct (REG) 195
- Register Indirect (REG) 196
- Indexed (INDX) 197
- Extended (EXT) 197
- Immediate (IMMED) 198
- Relative (REL) 198
- IO (I/O) 199
- DC Characteristics 200
- Z80180 DC CHARACTERISTICS 201
- Z8S180 DC CHARACTERISTICS 202
- Z8L180 DC CHARACTERISTICS 204
- AC Characteristics 208
- Timing Diagrams 213
- STANDARD TEST CONDITIONS 221
- Instruction Set 223
- CONDITION 224
- RESTART ADDRESS 225
- MISCELLANEOUS 226
- DATA TRANSFER INSTRUCTIONS 238
- Special Control Instructions 251
- Instruction Summary 253
- Op Code Map 263
- DDH 22H : LD (mn), IX 264
- Bus Control Signal Conditions 267
- INTERRUPTS 295
- Operating Modes Summary 297
- REQUEST PRIORITY 298
- OPERATION MODE TRANSITION 299
- 0000H (all DMA transfers) 301
- Status Signals 303
- PIN STATUS 304
- –A17, A19 — Z 1 A 1 305
- –D7— ZZAZ 305
- INTERNAL I/O REGISTERS 309
- Ch 0 Destination Mode 1,0 315
- ORDERING INFORMATION 319
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