Zilog Z80180 Manual de usuario descargar pdf (Pagina 280)

100

101

Z8018x

Family MPU User Manual

264

UM005003-0703

LD (mn),A

MC1 T1T2T3 1st Op Code

Address

1st Op

Code

010 1 01 0

MC2 T1T2T3 1st operand

Address

n 010 1 11 1

MC3 T1T2T3 2nd operand

Address

m 010 1 11 1

MC4 Ti * Z 111 1 11 1

MC5 T1T2T3mn A 100 1 11 1

LD A,I

LD A,R

LD I,A

LD R,A

MC1 T1T2T3 1st Op Code

Address

1st Op

Code

010 1 01 0

MC2 T1T2T3 2nd Op Code

Address

2nd Op

Code

010 1 01 1

LD ww, mn

MC1 T1T2T3 1st Op Code

Address

1st Op

Code

010 1 01 0

MC2 T1T2T3 1st operand

Address

n 010 1 11 1

MC3 T1T2T3 2nd operand

Address

m 010 1 11 1

LD IX,mn

LD IY,mn

MC1 T1T2T3 1st Op Code

Address

1st Op

Code

010 1 01 0

MC2 T1T2T3 2nd Op Code

Address

2nd Op

Code

010 1 01 1

MC3 T1T2T3 1st operand

Address

n 010 1 11 1

MC4 T1T2T3 2nd operand

Address

m 010 1 11 1

*4 In the case of R1 and Z MASK, interrupt request is not sampled.

Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)

Instruction

Machine

Cycle States Address Data RD WR MREQ IORQ M1 HALT ST

1 2 ... 275 276 277 278 279 280 281 282 283 284 285 ... 325 326

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