Zilog Z80180 Manual de usuario descargar pdf (Pagina 38)

100

101

Z8018x

Family MPU User Manual

UM005003-0703

Figure 13. I/O Read/Write Timing Diagram

Basic Instruction Timing

An instruction may consist of a number of machine cycles including Op

Code fetch, operand fetch, and data read/write cycles. An instruction may

also include cycles for internal processes which make the bus IDLE. The

example in Figure 14 illustrates the bus timing for the data transfer

instruction LD (IX+d),g.

T1 T1T2 TW T3 T2 T3

Phi

–

A19

–

IORQ

WAIT

I/O Read Cycle

I/O Write Cycle

Write data

I/O address

Read data

1 2 ... 33 34 35 36 37 38 39 40 41 42 43 ... 325 326

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Zilog Z80180 Manual de usuario Pagina 38

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