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Z8018x
Family MPU User Manual
247
UM005003-0703
Op Code Map
Table 48. 1st Op Code Map Instruction Format: XX
ww (L0 = ALL) L0 = 0~7
BC DE HL SP BC DE HL AF zz
g (LO = 0~7) NZ NC P0 P f
B D H (HL) B D H (HL) 00H 10H 20H 30H v
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
0 1234567 8 9 A B C D E F
S (HI = ALL)
B 0000 0 N0P DJNZj JR
NZ,j
JR
NC,j
LD g, s
note 1)
ADD
A,s
SUB s AND s OR s
RET f 0
C 0001 1 LD ww, mn POP zz 1
D 0010 2 LD (ww), A LD
(mn)
,HL
LD
(mn),
A
JP f, mn 2
E 0011 3 INC ww JP mn OUT
(m),A
EX(SP),
HL
DI 3
H 0100 4 INC g note1 CALL f, mn 4
L 0101 5 DEC g note1 PUSH zz 5
(HL) 0110 6 LD g,m note1 note2 HALT note2 note2 note2 note2 ADD
A,m
SUB m AND m OR m 6
A 0111 7 RLCA RLA DAA SCF RST v 7
B 1000 8 EXAF,A
F’
JR j JR Z,j JR C,j
LD g, s ADC
A,s
SBC
A,s
XOR s CP s
RE T f
8
C 1001 9 ADD HL, ww RET EXX JP(HL) LD
SP,
HL
9
D 1010 A LD A,(ww) LD
HL,
(mn)
LD A,
(mn)
JP f, mn A
E 1011 B DEC ww Table2 IN A(m) EXDE,H
L
EI B
H 1100 C INC g CALL f, mn C
L 1101 D DEC g CALL
mn
note3 Table3 note3 D
(HL) 1110 E LD g,m note2 note2 note2 note2 note2 ADC
A,m
SBC A,m XOR m CP m E
A 1111 F RRCA RRA CPL CCF RST v F
0 1234567 8 9 A B C D E F
C ELACELA Z C PE Mf
g(L0 = 8~F) 08H 18H 28H 3BH v
LO = 8~F
LO
HI
- Family MPU 1
- MANUAL OBJECTIVES 3
- Intended Audience 3
- Manual Organization 3
- Sections 4
- Appendices 4
- Table of Contents 5
- List of Figures 8
- UM005003-0703 10
- List of Tables 12
- Status Signals 287 14
- FEATURES 16
- GENERAL DESCRIPTION 16
- PIN DESCRIPTION 22
- ARCHITECTURE 27
- OPERATION MODES 30
- 0 and IOC is 0 32
- CPU Timing 33
- Wait State Generator 42
- Bit 7 6 5 4 44
- MWI1 MWI0 MWI1 MWI0 44
- R/W R/W R/W R/W 44
- 1, selecting the 45
- Processors Only) 46
- SLP 2nd Op Code address 50
- Add-On Features 51
- STANDBY Mode 52
- IDLE Mode 55
- STANDBY-QUICK RECOVERY Mode 56
- Internal I/O Registers 56
- –0 Reserved ? ? Reserved 67
- Memory Management Unit (MMU) 69
- Figure 25. MMU Block Diagram 71
- 0 during I/O cycles 72
- MMU Register Description 75
- 0 during RESET 77
- 1 while all bits 78
- 0. The logical 64KB 78
- 0000H to FFFFH) 78
- Interrupts 80
- Interrupt Vector Low Register 81
- 00H during RESET 82
- N/A R/W R/W R/W 83
- 1 by the El (Enable 84
- 00000H was caused by 85
- INT0 Mode 0 90
- INT0 Mode 1 91
- INT0 Mode 2 93
- 00H and 94
- INT1, INT2 95
- 0. Each is also 96
- Family MPU User Manual 100
- Dynamic RAM Refresh Control 101
- TR1 TRW* TR2 102
- DMA Controller (DMAC) 105
- 107
- DMAC Register Description 108
- DMA Register Description 118
- Bits 5–3 119
- Bits 2–0 119
- DMA Operation 119
- Memory to Memory—Channel 0 120
- 00H) transfer 122
- Memory to ASCI - Channel 0 124
- Note: X = Don’t care 125
- T1 T2 T3 T3T2T1 130
- Processors 131
- ASCI Register Description 132
- 08H, 09H) 134
- 1) these pins 149
- 1, then the CKA1/ 149
- 0. Even after the 154
- Figure 56. ASCI Clock 156
- Baud Rate Generator 158
- CSI/O Block Diagram 161
- CSI/O Registers Description 162
- Address = 0BH) 164
- Interrupt Request 166
- = 0) when 167
- PRT Block Diagram 171
- PRT Register Description 172
- 0FH, CHI, 16H, 17H) 174
- Timer Control Register (TCR) 176
- PRT Interrupts 179
- PRT and RESET 179
- Secondary Bus Interface 180
- On-Chip Clock Generator 183
- Miscellaneous 187
- Software Architecture 188
- CPU REGISTERS 190
- Accumulator (A, A') 191
- Flag Registers (F, F') 192
- Interrupt Vector Register (I) 192
- R Counter (R) 192
- Index Registers (IX, and IY) 192
- Stack Pointer (SP) 193
- Program Counter (PC) 193
- Flag Register (F) 193
- Addressing Modes 195
- Implied Register (IMP) 195
- Register Direct (REG) 195
- Register Indirect (REG) 196
- Indexed (INDX) 197
- Extended (EXT) 197
- Immediate (IMMED) 198
- Relative (REL) 198
- IO (I/O) 199
- DC Characteristics 200
- Z80180 DC CHARACTERISTICS 201
- Z8S180 DC CHARACTERISTICS 202
- Z8L180 DC CHARACTERISTICS 204
- AC Characteristics 208
- Timing Diagrams 213
- STANDARD TEST CONDITIONS 221
- Instruction Set 223
- CONDITION 224
- RESTART ADDRESS 225
- MISCELLANEOUS 226
- DATA TRANSFER INSTRUCTIONS 238
- Special Control Instructions 251
- Instruction Summary 253
- Op Code Map 263
- DDH 22H : LD (mn), IX 264
- Bus Control Signal Conditions 267
- INTERRUPTS 295
- Operating Modes Summary 297
- REQUEST PRIORITY 298
- OPERATION MODE TRANSITION 299
- 0000H (all DMA transfers) 301
- Status Signals 303
- PIN STATUS 304
- –A17, A19 — Z 1 A 1 305
- –D7— ZZAZ 305
- INTERNAL I/O REGISTERS 309
- Ch 0 Destination Mode 1,0 315
- ORDERING INFORMATION 319
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